Mercurial > public > hwos_code
annotate src/hwos.asm @ 389:9175429bdeba
CHANGE: Logbook now shows end-of-dive date and time for dives made with firmware <1.92 indicated by an icon in the logbook
CHANGE: Logbook shows start-of-dive date and time for dives made with firmware >=1.92
BUGFIX: Text alignment in logbook
| author | heinrichsweikamp |
|---|---|
| date | Tue, 27 Oct 2015 13:45:10 +0100 |
| parents | c64ffeeb86e5 |
| children | aadfe9f2edaf |
| rev | line source |
|---|---|
| 0 | 1 ;============================================================================= |
| 2 ; | |
| 275 | 3 ; File hwos.asm |
| 0 | 4 ; |
| 275 | 5 ; Definition of the hwOS dive computer platform. |
| 0 | 6 ; |
| 7 ; Copyright (c) 2011, JD Gascuel, HeinrichsWeikamp, all right reserved. | |
| 8 ;============================================================================= | |
| 9 ; HISTORY | |
| 10 ; 2011-05-24 : [jDG] Cleanups from initial Matthias code. | |
| 11 ; 2011-06-24 : [MH] Added clock speeds. | |
| 275 | 12 #include "hwos.inc" |
| 0 | 13 |
| 14 ;============================================================================= | |
| 15 ;----------------------------- CONFIG --------------------------------- | |
| 1 | 16 CONFIG RETEN = OFF ;Disabled - Controlled by SRETEN bit |
| 17 CONFIG SOSCSEL = HIGH ;High Power SOSC circuit selected | |
| 199 | 18 CONFIG XINST = OFF ;Code won't excute in extended mode... |
| 1 | 19 CONFIG FOSC = INTIO2 ;Internal RC oscillator, no clock-out |
| 20 CONFIG PLLCFG = OFF | |
| 21 CONFIG IESO = OFF ;Disabled | |
| 22 CONFIG PWRTEN = OFF ;Disabled, because incompatible with ICD3 (Ri-400) | |
| 23 CONFIG BOREN = ON ;Controlled with SBOREN bit | |
| 24 CONFIG BORV = 2 ;2.0V | |
| 25 CONFIG BORPWR = MEDIUM ;BORMV set to medium power level | |
| 26 CONFIG WDTEN = ON ;WDT controlled by SWDTEN bit setting | |
| 27 CONFIG WDTPS = 128 ;1:128 | |
| 28 CONFIG RTCOSC = SOSCREF ;RTCC uses SOSC | |
| 29 CONFIG MCLRE = ON ;MCLR Enabled, RG5 Disabled | |
| 30 CONFIG CCP2MX = PORTBE ;RE7-Microcontroller Mode/RB3-All other modes | |
| 0 | 31 ;============================================================================= |
| 32 boot CODE | |
| 275 | 33 global init_ostc |
| 0 | 34 |
| 275 | 35 init_ostc: |
| 0 | 36 banksel common ; Bank1 |
| 37 ;init oscillator | |
| 38 movlw b'01110010' | |
| 39 movwf OSCCON ; 16MHz INTOSC | |
| 40 movlw b'00001000' | |
| 41 movwf OSCCON2 ; Secondary Oscillator running | |
| 42 movlw b'00000000' | |
| 43 movwf OSCTUNE ; 4x PLL Disable (Bit6) - only works with 8 or 16MHz (=32 or 64MHz) | |
| 44 bcf RCON,SBOREN ; Bown-Out off | |
| 45 bcf RCON,IPEN ; Priority Interrupts off | |
| 209 | 46 clrf CM1CON ; Disable |
| 199 | 47 banksel WDTCON |
| 48 movlw b'10000000' | |
| 49 movwf WDTCON ; Setup Watchdog | |
| 0 | 50 |
| 51 ; I/O Ports | |
| 52 banksel 0xF16 ; Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM. | |
| 53 | |
| 54 clrf REFOCON ; No reference oscillator active on REFO pin | |
| 55 clrf ODCON1 ; Disable Open Drain capability | |
| 56 clrf ODCON2 ; Disable Open Drain capability | |
| 57 clrf ODCON3 ; Disable Open Drain capability | |
| 209 | 58 clrf CM2CON ; Disable |
| 59 clrf CM3CON ; Disable | |
| 0 | 60 |
| 61 movlw b'11000000' ; ANSEL, AN7 and AN6 -> Analog inputs, PORTA is digital. | |
| 62 movwf ANCON0 | |
| 113 | 63 movlw b'00000111' ; ANSEL, AN8, AN9, AN10 -> Analog in |
| 0 | 64 movwf ANCON1 |
| 65 movlw b'00000010' ; ANSEL, AN17 -> Analog input | |
| 66 movwf ANCON2 | |
| 67 | |
| 68 banksel common | |
| 69 | |
| 70 movlw b'00000000' ; 1= Input -> Data TFT_high | |
| 71 movwf TRISA | |
| 72 movlw b'00000000' ; Init port | |
| 73 movwf PORTA | |
| 74 | |
| 113 | 75 movlw b'00000011' ; 1= Input, (RB0, RB1) -> Switches, RB2 -> Power_MCP, RB3 -> s8_npower, RB4 -> LED_green, RB5 -> /TFT_POWER |
| 0 | 76 movwf TRISB |
| 113 | 77 movlw b'00101000' ; Init port |
| 0 | 78 movwf PORTB |
| 79 | |
| 80 movlw b'10011010' ; 1= Input, (RC0, RC1) -> SOSC, RC2 -> TFT_LED_PWM, (RC3,RC4) -> I²C, RC5 -> MOSI_MS5541, (RC6, RC7) -> UART1 | |
| 81 movwf TRISC | |
| 82 movlw b'00000000' ; Init port | |
| 83 movwf PORTC | |
| 84 | |
| 85 movlw b'00100000' ; 1= Input, RD0 -> TFT_NCS, RD1 -> TFT_RS, RD2 -> TFT_NWR, RD3 -> TFT_RD, RD4 -> MOSI_Flash, RD5 -> MISO_Flash, RD6 -> CLK_Flash, RD7 -> TFT_NRESET | |
| 86 movwf TRISD | |
| 87 movlw b'00000000' ; Init port | |
| 88 movwf PORTD | |
| 89 | |
| 200 | 90 movlw b'00000000' ; 1= Input, RE1 -> Power_IR, RE2 -> CS_MCP, RE3 -> LED_blue, RE4 -> power_sw1, RE5 -> Set to 1 for cR hardware |
| 0 | 91 movwf TRISE |
| 209 | 92 movlw b'00110001' ; Init port |
| 0 | 93 movwf PORTE |
| 94 | |
| 209 | 95 movlw b'01111110' ; 1= Input, (RF1, RF2, RF3, RF4, RF5) -> Analog |
| 0 | 96 movwf TRISF |
| 97 movlw b'00000000' ; Init port | |
| 98 movwf PORTF | |
| 99 | |
| 113 | 100 movlw b'00001110' ; 1= Input, <7:6> not implemented, RG0 -> TX3_PIEZO_CFG, RG2 -> RX2, RG3 -> AN17_RSSI, RG4 -> SOSC_OUT, RG5 -> /RESET |
| 0 | 101 movwf TRISG |
| 113 | 102 movlw b'00000001' ; Init port |
| 0 | 103 movwf PORTG |
| 104 | |
| 105 movlw b'00000000' ; 1= Input -> Data TFT_low | |
| 106 movwf TRISH | |
| 107 movlw b'00000000' ; Init port | |
| 108 movwf PORTH | |
| 109 | |
| 120 | 110 movlw b'10011011' ; 1= Input, RJ4 -> vusb_in, RJ5 -> power_sw2, RJ6 -> CLK_MS5541, RJ7 -> MISO_MS5541 |
| 0 | 111 movwf TRISJ |
| 112 movlw b'00100000' ; Init port | |
| 113 movwf PORTJ | |
| 114 | |
| 115 | |
| 116 ; Timer 0 | |
| 28 | 117 movlw b'00000001' ; Timer0 with 1:4 prescaler |
| 0 | 118 movwf T0CON |
| 119 | |
| 120 ; Timer 1 - Button hold-down timer | |
| 121 movlw b'10001100' ; 32768Hz clock source, 1:1 Prescaler -> ; 30,51757813µs/bit in TMR1L:TMR1H | |
| 122 movwf T1CON | |
| 123 | |
| 124 banksel 0xF16 ; Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM. | |
| 125 | |
| 126 ; RTCC | |
| 127 movlw 0x55 | |
| 128 movwf EECON2 | |
| 129 movlw 0xAA | |
| 130 movwf EECON2 | |
| 131 bsf RTCCFG,RTCWREN ; Unlock sequence for RTCWREN | |
| 132 bsf RTCCFG,RTCPTR1 | |
| 133 bsf RTCCFG,RTCPTR0 | |
| 134 bsf RTCCFG,RTCEN ; Module enable | |
| 135 bsf RTCCFG,RTCOE ; Output enable | |
| 136 movlw b'00000100' ; 32768Hz SOCS on RTCC pin (PORTG,4) Bit7-5: Pullups for Port D, E and J | |
| 137 movwf PADCFG1 | |
| 138 movlw b'11000100' | |
| 139 movwf ALRMCFG ; 1 second alarm | |
| 140 movlw d'1' | |
| 141 movwf ALRMRPT ; Alarm repeat counter | |
| 142 movlw 0x55 | |
| 143 movwf EECON2 | |
| 144 movlw 0xAA | |
| 145 movwf EECON2 | |
| 146 bcf RTCCFG,RTCWREN ; Lock sequence for RTCWREN | |
| 147 | |
| 148 banksel common | |
| 149 ; A/D Converter | |
| 150 movlw b'00011000' ; power off ADC, select AN6 | |
| 151 movwf ADCON0 | |
| 152 movlw b'00100000' ; 2.048V Vref+ | |
| 153 movwf ADCON1 | |
| 154 movlw b'10001101' ; Right justified | |
| 155 movwf ADCON2 | |
| 156 | |
| 157 | |
| 158 ;init serial port1 (TRISC6/7) | |
| 159 movlw b'00001000' ; BRG16=1 | |
| 160 movwf BAUDCON1 | |
| 161 movlw .34 ; SPBRGH:SPBRG = .34 : 114285 BAUD @ 16MHz (+0,79% Error to 115200 BAUD) | |
| 162 movwf SPBRG1 ; SPBRGH:SPBRG = .207 : 19230 BAUD @ 16MHz (-0,16% Error to 19200 BAUD) | |
| 163 clrf SPBRGH1 ; | |
| 204 | 164 |
| 165 clrf RCSTA1 | |
| 166 clrf TXSTA1 ; UART disable | |
| 167 bcf PORTC,6 ; TX hard to GND | |
| 0 | 168 |
| 169 ;init serial port2 (TRISG2) | |
| 170 banksel BAUDCON2 | |
| 113 | 171 movlw b'00100000' ; BRG16=0 ; inverted for IR |
| 0 | 172 movwf BAUDCON2 |
| 173 movlw b'00100000' ; BRGH=0, SYNC=0 | |
| 174 movwf TXSTA2 | |
| 175 movlw .102 ; SPBRGH:SPBRG = .102 : 2403 BAUD @ 16MHz | |
| 176 movwf SPBRG2 | |
| 177 clrf SPBRGH2 | |
| 178 movlw b'10010000' | |
| 179 movwf RCSTA2 | |
| 180 banksel common | |
| 181 | |
| 182 ; Timer3 for IR-RX Timeout | |
| 183 clrf T3GCON ; Reset Timer3 Gate Control register | |
| 184 movlw b'10001001' ; 1:1 Prescaler -> 2seconds@32768Hz, synced | |
| 185 ; 30,51757813µs/bit in TMR3L:TMR3H | |
| 186 movwf T3CON | |
| 187 | |
| 188 ; SPI Module(s) | |
| 189 ; SPI2: External Flash | |
| 190 movlw b'00110000' | |
| 191 movwf SSP2CON1 | |
| 192 movlw b'00000000' | |
| 193 movwf SSP2STAT | |
| 194 ; ->0,25MHz Bit clock @1MHz mode (Eco) | |
| 195 ; -> 4MHz Bit clock @16MHz mode (Normal) | |
| 196 ; -> 16MHz Bit clock @64MHz mode (Fastest) | |
| 197 | |
| 198 ; MSSP1 Module: I2C Master | |
| 199 movlw b'00101000' ; I2C Master Mode | |
| 200 movwf SSP1CON1 | |
| 201 movlw b'00000000' | |
| 202 movwf SSP1CON2 | |
| 203 movlw 0x27 | |
| 204 movwf SSP1ADD ; 100kHz @ 16MHz Fosc | |
| 205 | |
| 206 ; PWM Module(s) | |
| 207 ; PWM1 for LED dimming | |
| 208 movlw b'00001100' | |
| 209 movwf CCP1CON | |
| 210 movlw b'00000001' | |
| 211 movwf PSTR1CON ; Pulse steering disabled | |
| 212 movlw d'255' | |
| 213 movwf PR2 ; Period | |
| 214 ; 255 is max brightness (300mW) | |
| 215 clrf CCPR1L ; Duty cycle | |
| 216 clrf CCPR1H ; Duty cycle | |
| 217 movlw T2CON_NORMAL | |
| 218 movwf T2CON | |
| 219 | |
| 220 ; Timer5 for ISR-independent wait routines | |
| 221 clrf T5GCON ; Reset Timer5 Gate Control register | |
| 222 movlw b'10001001' ; 1:1 Prescaler -> 2seconds@32768Hz, synced | |
| 223 ; 30,51757813µs/bit in TMR5L:TMR5H | |
| 224 movwf T5CON | |
| 225 | |
| 226 ; Timer7 for 62,5ms Interrupt (Sensor states) | |
| 227 banksel 0xF16 ; Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM. | |
| 228 clrf T7GCON ; Reset Timer7 Gate Control register | |
| 229 movlw b'10001001' ; 1:1 Prescaler -> 2seconds@32768Hz, synced | |
| 230 movwf T7CON | |
| 231 clrf TMR7L | |
| 232 movlw .248 | |
| 233 movwf TMR7H ; -> Rollover after 2048 cycles -> 62,5ms | |
| 234 | |
| 235 banksel common | |
| 236 ; Interrupts | |
| 50 | 237 movlw b'11010000' |
| 0 | 238 movwf INTCON |
|
77
131e6dd9e201
BUGFIX: Potential bug to freeze the OSTC3 after battery change or update
heinrichsweikamp
parents:
58
diff
changeset
|
239 movlw b'00001000' ; BIT7=1: Pullup for PORTB disabled |
| 0 | 240 movwf INTCON2 |
|
77
131e6dd9e201
BUGFIX: Potential bug to freeze the OSTC3 after battery change or update
heinrichsweikamp
parents:
58
diff
changeset
|
241 movlw b'00000000' |
| 0 | 242 movwf INTCON3 |
| 243 movlw b'00000001' ; Bit0: TMR1 | |
| 244 movwf PIE1 | |
| 245 movlw b'00000010' ; Bit1: TMR3 | |
| 246 movwf PIE2 | |
| 247 movlw b'00000000' ; Bit1: TMR5 | |
| 248 movwf PIE5 | |
| 249 movlw b'00100001' ; Bit0: RTCC, Bit5: UART2 | |
| 250 movwf PIE3 | |
| 251 movlw b'00001000' ; Bit3: TMR7 | |
| 252 movwf PIE5 | |
| 253 | |
| 254 bsf power_sw1 | |
| 58 | 255 btfss power_sw1 |
| 256 bra $-4 | |
| 0 | 257 bsf power_sw2 |
| 58 | 258 btfss power_sw2 |
| 259 bra $-4 | |
| 0 | 260 |
| 204 | 261 movlw d'2' |
| 319 | 262 movff WREG,speed_setting ; Normal |
| 204 | 263 |
| 264 | |
| 0 | 265 return |
| 266 | |
| 267 ;============================================================================= | |
| 268 global speed_eco | |
| 269 speed_eco: | |
| 270 movlw d'1' | |
| 271 movff WREG,speed_setting ; Bank-independent | |
| 272 ; Done in ISR | |
| 273 return | |
| 274 ;============================================================================= | |
| 275 global speed_normal | |
| 276 speed_normal: | |
| 277 movlw d'2' | |
| 278 movff WREG,speed_setting ; Bank-independent | |
| 279 ; Done in ISR | |
| 280 return | |
| 281 ;============================================================================= | |
| 282 global speed_fastest | |
| 283 speed_fastest: | |
| 284 movlw d'3' | |
| 285 movff WREG,speed_setting ; Bank-independent | |
| 286 ; Done in ISR | |
| 287 return | |
| 288 ;============================================================================= | |
| 289 | |
| 290 END |