Mercurial > public > hwos_code
annotate src/hwos.asm @ 606:8b250afb8bdd
minor
| author | heinrichsweikamp |
|---|---|
| date | Sun, 25 Nov 2018 15:15:27 +0100 |
| parents | ca4556fb60b9 |
| children | d866684249bd |
| rev | line source |
|---|---|
| 0 | 1 ;============================================================================= |
| 2 ; | |
| 604 | 3 ; File hwos.asm V2.98c |
| 0 | 4 ; |
| 275 | 5 ; Definition of the hwOS dive computer platform. |
| 0 | 6 ; |
| 7 ; Copyright (c) 2011, JD Gascuel, HeinrichsWeikamp, all right reserved. | |
| 8 ;============================================================================= | |
| 9 ; HISTORY | |
| 604 | 10 ; 2011-05-24 : [jDG] Cleanups from initial Matthias code |
| 11 ; 2011-06-24 : [MH] Added clock speeds | |
| 12 | |
| 13 | |
| 275 | 14 #include "hwos.inc" |
| 0 | 15 |
| 16 ;============================================================================= | |
| 17 ;----------------------------- CONFIG --------------------------------- | |
| 604 | 18 CONFIG RETEN = OFF ; disabled - controlled by SRETEN bit |
| 19 CONFIG SOSCSEL = HIGH ; High Power SOSC circuit selected | |
| 20 CONFIG XINST = OFF ; code won't execute in extended mode | |
| 21 CONFIG FOSC = INTIO2 ; internal RC oscillator, no clock-out | |
| 22 CONFIG PLLCFG = OFF | |
| 23 CONFIG IESO = OFF ; disabled | |
| 24 CONFIG PWRTEN = OFF ; disabled, because incompatible with ICD3 (Ri-400) | |
| 25 CONFIG BOREN = ON ; controlled with SBOREN bit | |
| 26 CONFIG BORV = 2 ; 2.0V | |
| 27 CONFIG BORPWR = MEDIUM ; BORMV set to medium power level | |
| 28 CONFIG WDTEN = ON ; WDT controlled by SWDTEN bit setting | |
| 29 CONFIG WDTPS = 128 ; 1:128 | |
| 30 CONFIG RTCOSC = SOSCREF ; RTCC uses SOSC | |
| 31 CONFIG MCLRE = ON ; MCLR Enabled, RG5 Disabled | |
| 32 CONFIG CCP2MX = PORTBE ; RE7-microcontroller mode/RB3-all other modes | |
| 33 | |
| 34 hwos CODE | |
| 35 | |
| 0 | 36 ;============================================================================= |
| 37 | |
| 604 | 38 global init_ostc |
| 275 | 39 init_ostc: |
| 604 | 40 banksel common ; bank 1 |
| 41 ; init oscillator | |
| 0 | 42 movlw b'01110010' |
| 604 | 43 movwf OSCCON ; 16 MHz INTOSC |
| 0 | 44 movlw b'00001000' |
| 604 | 45 movwf OSCCON2 ; secondary oscillator running |
| 0 | 46 movlw b'00000000' |
| 604 | 47 movwf OSCTUNE ; 4x PLL disable (Bit 6) - only works with 8 or 16MHz (=32 or 64MHz) |
| 48 bcf RCON,SBOREN ; bown-out off | |
| 49 bcf RCON,IPEN ; priority interrupts off | |
| 50 clrf CM1CON ; disable | |
| 51 banksel WDTCON | |
| 52 movlw b'10000000' | |
| 53 movwf WDTCON ; setup watchdog | |
| 0 | 54 |
| 55 ; I/O Ports | |
| 604 | 56 banksel 0xF16 ; addresses, F16h through F5Fh, are also used by SFRs, but are not part of the access RAM |
| 0 | 57 |
| 604 | 58 clrf REFOCON ; no reference oscillator active on REFO pin |
| 59 clrf ODCON1 ; disable open drain capability | |
| 60 clrf ODCON2 ; disable open drain capability | |
| 61 clrf ODCON3 ; disable open drain capability | |
| 62 clrf CM2CON ; disable | |
| 63 clrf CM3CON ; disable | |
| 0 | 64 |
| 604 | 65 movlw b'11000000' ; ANSEL, AN7 and AN6 -> Analog inputs, PORTA is digital |
| 0 | 66 movwf ANCON0 |
| 604 | 67 movlw b'00000111' ; ANSEL, AN8, AN9, AN10 -> Analog input |
| 0 | 68 movwf ANCON1 |
| 69 movlw b'00000010' ; ANSEL, AN17 -> Analog input | |
| 70 movwf ANCON2 | |
| 71 | |
| 604 | 72 banksel common |
| 0 | 73 |
| 604 | 74 ; movlw b'00000000' ; 1= input -> Data TFT_high |
| 448 | 75 clrf TRISA |
| 604 | 76 ; movlw b'00000000' ; init port |
| 448 | 77 clrf PORTA |
| 0 | 78 |
| 604 | 79 movlw b'00000011' ; 1= input, (RB0, RB1) -> switches, RB2 -> Power_MCP, RB3 -> s8_npower, RB4 -> LED_green/rx_nreset, RB5 -> /TFT_POWER |
| 0 | 80 movwf TRISB |
| 604 | 81 movlw b'00111000' ; init port, rx_nreset=1 -> hard reset RX |
| 0 | 82 movwf PORTB |
| 83 | |
| 604 | 84 movlw b'10011010' ; 1= input, (RC0, RC1) -> SOSC, RC2 -> TFT_LED_PWM, (RC3,RC4) -> I²C, RC5 -> MOSI_MS5541, (RC6, RC7) -> UART1 |
| 0 | 85 movwf TRISC |
| 604 | 86 ; movlw b'00000000' ; init port |
| 448 | 87 clrf PORTC |
| 0 | 88 |
| 604 | 89 movlw b'00100000' ; 1= input, RD0 -> TFT_NCS, RD1 -> TFT_RS, RD2 -> TFT_NWR, RD3 -> TFT_RD, RD4 -> MOSI_Flash, RD5 -> MISO_Flash, RD6 -> CLK_Flash, RD7 -> TFT_NRESET |
| 0 | 90 movwf TRISD |
| 604 | 91 ; movlw b'00000000' ; init port |
| 448 | 92 clrf PORTD |
| 0 | 93 |
| 604 | 94 ; movlw b'00000000' ; 1= input, RE1 -> Power_IR, RE2 -> CS_MCP, RE3 -> LED_blue, RE4 -> power_sw1, RE5 -> Set to 1 for cR hardware |
| 448 | 95 clrf TRISE |
| 604 | 96 movlw b'00110001' ; init port |
| 0 | 97 movwf PORTE |
| 98 | |
| 604 | 99 movlw b'01111110' ; 1= input, (RF1, RF2, RF3, RF4, RF5) -> Analog |
| 0 | 100 movwf TRISF |
| 604 | 101 ; movlw b'00000000' ; init port |
| 448 | 102 clrf PORTF |
| 0 | 103 |
| 604 | 104 movlw b'00001110' ; 1= input, <7:6> not implemented, RG0 -> TX3_PIEZO_CFG, RG2 -> RX2, RG3 -> AN17_RSSI, RG4 -> SOSC_OUT, RG5 -> /RESET |
| 0 | 105 movwf TRISG |
| 604 | 106 movlw b'00000001' ; init port |
| 0 | 107 movwf PORTG |
| 108 | |
| 604 | 109 ; movlw b'00000000' ; 1= input -> Data TFT_low |
| 448 | 110 clrf TRISH |
| 604 | 111 ; movlw b'00000000' ; init port |
| 448 | 112 clrf PORTH |
| 0 | 113 |
| 604 | 114 movlw b'10011011' ; 1= input, RJ4 -> vusb_in, RJ5 -> power_sw2, RJ6 -> CLK_MS5541, RJ7 -> MISO_MS5541 |
| 0 | 115 movwf TRISJ |
| 604 | 116 movlw b'00100000' ; init port |
| 0 | 117 movwf PORTJ |
| 118 | |
| 119 | |
| 120 ; Timer 0 | |
| 604 | 121 movlw b'00000001' ; timer0 with 1:4 prescaler |
| 0 | 122 movwf T0CON |
| 123 | |
| 124 ; Timer 1 - Button hold-down timer | |
| 604 | 125 movlw b'10001100' ; 32768Hz clock source, 1:1 prescaler -> ; 30.51757813 µs/bit in TMR1L:TMR1H |
| 0 | 126 movwf T1CON |
| 127 | |
| 604 | 128 banksel 0xF16 ; addresses, F16h through F5Fh, are also used by SFRs, but are not part of the access RAM |
| 0 | 129 |
| 130 ; RTCC | |
| 604 | 131 movlw 0x55 |
| 132 movwf EECON2 | |
| 133 movlw 0xAA | |
| 134 movwf EECON2 | |
| 135 bsf RTCCFG,RTCWREN ; unlock sequence for RTCWREN | |
| 0 | 136 bsf RTCCFG,RTCPTR1 |
| 137 bsf RTCCFG,RTCPTR0 | |
| 604 | 138 bsf RTCCFG,RTCEN ; module enable |
| 139 bsf RTCCFG,RTCOE ; output enable | |
| 140 movlw b'00000100' ; 32768 Hz SOCS on RTCC pin (PORTG,4) Bit7-5: pullups for Port D, E and J | |
| 0 | 141 movwf PADCFG1 |
| 142 movlw b'11000100' | |
| 143 movwf ALRMCFG ; 1 second alarm | |
| 144 movlw d'1' | |
| 604 | 145 movwf ALRMRPT ; alarm repeat counter |
| 146 movlw 0x55 | |
| 147 movwf EECON2 | |
| 148 movlw 0xAA | |
| 149 movwf EECON2 | |
| 150 bcf RTCCFG,RTCWREN ; lock sequence for RTCWREN | |
| 0 | 151 |
| 152 banksel common | |
| 153 ; A/D Converter | |
| 154 movlw b'00011000' ; power off ADC, select AN6 | |
| 155 movwf ADCON0 | |
| 156 movlw b'00100000' ; 2.048V Vref+ | |
| 157 movwf ADCON1 | |
| 604 | 158 movlw b'10001101' ; right aligned |
| 0 | 159 movwf ADCON2 |
| 160 | |
| 161 | |
| 604 | 162 ; init serial port1 (TRISC6/7) |
| 0 | 163 movlw b'00001000' ; BRG16=1 |
| 164 movwf BAUDCON1 | |
| 604 | 165 movlw .34 ; SPBRGH:SPBRG = .34 : 114285 BAUD @ 16MHz (+0.79% Error to 115200 BAUD) |
| 166 movwf SPBRG1 ; SPBRGH:SPBRG = .207 : 19230 BAUD @ 16MHz (-0.16% Error to 19200 BAUD) | |
| 0 | 167 clrf SPBRGH1 ; |
| 204 | 168 |
| 169 clrf RCSTA1 | |
| 604 | 170 clrf TXSTA1 ; UART disable |
| 171 bcf PORTC,6 ; TX hard to GND | |
| 0 | 172 |
| 604 | 173 ; init serial port2 (TRISG2) |
| 174 banksel BAUDCON2 | |
| 175 movlw b'00100000' ; BRG16=0 ; inverted for IR | |
| 0 | 176 movwf BAUDCON2 |
| 604 | 177 movlw b'00100000' ; BRGH=0, SYNC=0 |
| 178 movwf TXSTA2 | |
| 179 movlw .102 ; SPBRGH:SPBRG = .102 : 2403 BAUD @ 16MHz | |
| 180 movwf SPBRG2 | |
| 0 | 181 clrf SPBRGH2 |
| 604 | 182 movlw b'10010000' |
| 183 movwf RCSTA2 | |
| 184 banksel common | |
| 0 | 185 |
| 186 ; Timer3 for IR-RX Timeout | |
| 604 | 187 clrf T3GCON ; reset Timer3 gate control register |
| 188 movlw b'10001001' ; 1:1 prescaler -> 2 seconds@32768Hz, synced | |
| 0 | 189 ; 30,51757813µs/bit in TMR3L:TMR3H |
| 190 movwf T3CON | |
| 191 | |
| 192 ; SPI Module(s) | |
| 193 ; SPI2: External Flash | |
| 194 movlw b'00110000' | |
| 195 movwf SSP2CON1 | |
| 448 | 196 ; movlw b'00000000' |
| 197 clrf SSP2STAT | |
| 0 | 198 ; ->0,25MHz Bit clock @1MHz mode (Eco) |
| 199 ; -> 4MHz Bit clock @16MHz mode (Normal) | |
| 200 ; -> 16MHz Bit clock @64MHz mode (Fastest) | |
| 201 | |
| 202 ; MSSP1 Module: I2C Master | |
| 604 | 203 movlw b'00101000' ; I2C master mode |
| 0 | 204 movwf SSP1CON1 |
| 448 | 205 ; movlw b'00000000' |
| 206 clrf SSP1CON2 | |
| 0 | 207 movlw 0x27 |
| 604 | 208 movwf SSP1ADD ; 100kHz @ 16MHz Fosc |
| 0 | 209 |
| 210 ; PWM Module(s) | |
| 211 ; PWM1 for LED dimming | |
| 212 movlw b'00001100' | |
| 213 movwf CCP1CON | |
| 214 movlw b'00000001' | |
| 604 | 215 movwf PSTR1CON ; pulse steering disabled |
| 0 | 216 movlw d'255' |
| 604 | 217 movwf PR2 ; period |
| 218 ; 255 is max brightness (300 mW) | |
| 219 clrf CCPR1L ; duty cycle | |
| 220 clrf CCPR1H ; duty cycle | |
| 0 | 221 movlw T2CON_NORMAL |
| 222 movwf T2CON | |
| 223 | |
| 224 ; Timer5 for ISR-independent wait routines | |
| 604 | 225 clrf T5GCON ; reset Timer5 gate control register |
| 226 movlw b'10001001' ; 1:1 prescaler -> 2 seconds@32768Hz, synced | |
| 0 | 227 ; 30,51757813µs/bit in TMR5L:TMR5H |
| 228 movwf T5CON | |
| 229 | |
| 230 ; Timer7 for 62,5ms Interrupt (Sensor states) | |
| 604 | 231 banksel 0xF16 ; addresses, F16h through F5Fh, are also used by SFRs, but are not part of the access RAM |
| 232 clrf T7GCON ; reset Timer7 gate control register | |
| 233 movlw b'10001001' ; 1:1 prescaler -> 2 seconds@32768Hz, synced | |
| 0 | 234 movwf T7CON |
| 235 clrf TMR7L | |
| 236 movlw .248 | |
| 237 movwf TMR7H ; -> Rollover after 2048 cycles -> 62,5ms | |
| 238 | |
| 604 | 239 banksel common |
| 0 | 240 ; Interrupts |
| 50 | 241 movlw b'11010000' |
| 0 | 242 movwf INTCON |
| 604 | 243 movlw b'00001000' ; BIT7=1: pullup for PORTB disabled |
| 0 | 244 movwf INTCON2 |
|
77
131e6dd9e201
BUGFIX: Potential bug to freeze the OSTC3 after battery change or update
heinrichsweikamp
parents:
58
diff
changeset
|
245 movlw b'00000000' |
| 0 | 246 movwf INTCON3 |
| 247 movlw b'00000001' ; Bit0: TMR1 | |
| 248 movwf PIE1 | |
| 249 movlw b'00000010' ; Bit1: TMR3 | |
| 604 | 250 movwf PIE2 |
| 0 | 251 movlw b'00000000' ; Bit1: TMR5 |
| 252 movwf PIE5 | |
| 253 movlw b'00100001' ; Bit0: RTCC, Bit5: UART2 | |
| 254 movwf PIE3 | |
| 255 movlw b'00001000' ; Bit3: TMR7 | |
| 256 movwf PIE5 | |
| 257 | |
| 604 | 258 bsf power_sw1 |
| 259 btfss power_sw1 | |
| 260 bra $-4 | |
| 261 bsf power_sw2 | |
| 262 btfss power_sw2 | |
| 263 bra $-4 | |
| 0 | 264 |
| 204 | 265 movlw d'2' |
| 604 | 266 movff WREG,speed_setting ; normal |
| 204 | 267 |
| 604 | 268 bcf active_reset_ostc_rx ; start RX from RESET |
| 204 | 269 |
| 0 | 270 return |
| 271 | |
| 272 ;============================================================================= | |
| 273 global speed_eco | |
| 274 speed_eco: | |
| 275 movlw d'1' | |
| 604 | 276 movff WREG,speed_setting ; bank-independent |
| 0 | 277 ; Done in ISR |
| 278 return | |
| 279 ;============================================================================= | |
| 280 global speed_normal | |
| 281 speed_normal: | |
| 282 movlw d'2' | |
| 604 | 283 movff WREG,speed_setting ; bank-independent |
| 0 | 284 ; Done in ISR |
| 285 return | |
| 286 ;============================================================================= | |
| 287 global speed_fastest | |
| 288 speed_fastest: | |
| 289 movlw d'3' | |
| 604 | 290 movff WREG,speed_setting ; bank-independent |
| 0 | 291 ; Done in ISR |
| 292 return | |
| 293 ;============================================================================= | |
| 294 | |
| 604 | 295 END |