Mercurial > public > hwos_code
annotate src/hwos.asm @ 613:8077ee960199
fix for italian and french language
| author | heinrichsweikamp |
|---|---|
| date | Wed, 30 Jan 2019 16:27:56 +0100 |
| parents | 6dd6b37da7c8 |
| children | a32212cd5ea9 |
| rev | line source |
|---|---|
| 0 | 1 ;============================================================================= |
| 2 ; | |
| 608 | 3 ; File hwos.asm V2.98f |
| 0 | 4 ; |
| 275 | 5 ; Definition of the hwOS dive computer platform. |
| 0 | 6 ; |
| 7 ; Copyright (c) 2011, JD Gascuel, HeinrichsWeikamp, all right reserved. | |
| 8 ;============================================================================= | |
| 9 ; HISTORY | |
| 604 | 10 ; 2011-05-24 : [jDG] Cleanups from initial Matthias code |
| 11 ; 2011-06-24 : [MH] Added clock speeds | |
| 12 | |
| 13 | |
| 275 | 14 #include "hwos.inc" |
| 0 | 15 |
| 16 ;============================================================================= | |
| 17 ;----------------------------- CONFIG --------------------------------- | |
| 604 | 18 CONFIG RETEN = OFF ; disabled - controlled by SRETEN bit |
| 19 CONFIG SOSCSEL = HIGH ; High Power SOSC circuit selected | |
| 20 CONFIG XINST = OFF ; code won't execute in extended mode | |
| 21 CONFIG FOSC = INTIO2 ; internal RC oscillator, no clock-out | |
| 22 CONFIG PLLCFG = OFF | |
| 23 CONFIG IESO = OFF ; disabled | |
| 24 CONFIG PWRTEN = OFF ; disabled, because incompatible with ICD3 (Ri-400) | |
| 25 CONFIG BOREN = ON ; controlled with SBOREN bit | |
| 26 CONFIG BORV = 2 ; 2.0V | |
| 27 CONFIG BORPWR = MEDIUM ; BORMV set to medium power level | |
| 28 CONFIG WDTEN = ON ; WDT controlled by SWDTEN bit setting | |
| 29 CONFIG WDTPS = 128 ; 1:128 | |
| 30 CONFIG RTCOSC = SOSCREF ; RTCC uses SOSC | |
| 31 CONFIG MCLRE = ON ; MCLR Enabled, RG5 Disabled | |
| 32 CONFIG CCP2MX = PORTBE ; RE7-microcontroller mode/RB3-all other modes | |
| 33 | |
| 34 hwos CODE | |
| 35 | |
| 0 | 36 ;============================================================================= |
| 37 | |
| 604 | 38 global init_ostc |
| 275 | 39 init_ostc: |
| 608 | 40 ; init oscillator |
| 604 | 41 banksel common ; bank 1 |
| 0 | 42 movlw b'01110010' |
| 604 | 43 movwf OSCCON ; 16 MHz INTOSC |
| 0 | 44 movlw b'00001000' |
| 604 | 45 movwf OSCCON2 ; secondary oscillator running |
| 0 | 46 movlw b'00000000' |
| 604 | 47 movwf OSCTUNE ; 4x PLL disable (Bit 6) - only works with 8 or 16MHz (=32 or 64MHz) |
| 608 | 48 |
| 49 movlw d'2' ; coding for speed normal | |
| 50 movff WREG,cpu_speed_request ; CPU shall run with normal speed | |
| 51 movff WREG,cpu_speed_state ; CPU does run with normal speed | |
| 52 | |
| 612 | 53 ; bcf RCON,SBOREN ; brown-out off (Not needed, set in bootloader) |
| 604 | 54 bcf RCON,IPEN ; priority interrupts off |
| 608 | 55 |
| 604 | 56 banksel WDTCON |
| 57 movlw b'10000000' | |
| 58 movwf WDTCON ; setup watchdog | |
| 0 | 59 |
| 608 | 60 |
| 0 | 61 ; I/O Ports |
| 604 | 62 banksel 0xF16 ; addresses, F16h through F5Fh, are also used by SFRs, but are not part of the access RAM |
| 0 | 63 |
| 604 | 64 clrf REFOCON ; no reference oscillator active on REFO pin |
| 65 clrf ODCON1 ; disable open drain capability | |
| 66 clrf ODCON2 ; disable open drain capability | |
| 67 clrf ODCON3 ; disable open drain capability | |
| 608 | 68 clrf CM1CON ; disable |
| 604 | 69 clrf CM2CON ; disable |
| 70 clrf CM3CON ; disable | |
| 0 | 71 |
| 604 | 72 movlw b'11000000' ; ANSEL, AN7 and AN6 -> Analog inputs, PORTA is digital |
| 0 | 73 movwf ANCON0 |
| 604 | 74 movlw b'00000111' ; ANSEL, AN8, AN9, AN10 -> Analog input |
| 0 | 75 movwf ANCON1 |
| 76 movlw b'00000010' ; ANSEL, AN17 -> Analog input | |
| 77 movwf ANCON2 | |
| 78 | |
| 604 | 79 banksel common |
| 0 | 80 |
| 604 | 81 ; movlw b'00000000' ; 1= input -> Data TFT_high |
| 448 | 82 clrf TRISA |
| 604 | 83 ; movlw b'00000000' ; init port |
| 448 | 84 clrf PORTA |
| 0 | 85 |
| 604 | 86 movlw b'00000011' ; 1= input, (RB0, RB1) -> switches, RB2 -> Power_MCP, RB3 -> s8_npower, RB4 -> LED_green/rx_nreset, RB5 -> /TFT_POWER |
| 0 | 87 movwf TRISB |
| 604 | 88 movlw b'00111000' ; init port, rx_nreset=1 -> hard reset RX |
| 0 | 89 movwf PORTB |
| 90 | |
| 604 | 91 movlw b'10011010' ; 1= input, (RC0, RC1) -> SOSC, RC2 -> TFT_LED_PWM, (RC3,RC4) -> I²C, RC5 -> MOSI_MS5541, (RC6, RC7) -> UART1 |
| 0 | 92 movwf TRISC |
| 604 | 93 ; movlw b'00000000' ; init port |
| 448 | 94 clrf PORTC |
| 0 | 95 |
| 604 | 96 movlw b'00100000' ; 1= input, RD0 -> TFT_NCS, RD1 -> TFT_RS, RD2 -> TFT_NWR, RD3 -> TFT_RD, RD4 -> MOSI_Flash, RD5 -> MISO_Flash, RD6 -> CLK_Flash, RD7 -> TFT_NRESET |
| 0 | 97 movwf TRISD |
| 604 | 98 ; movlw b'00000000' ; init port |
| 448 | 99 clrf PORTD |
| 0 | 100 |
| 604 | 101 ; movlw b'00000000' ; 1= input, RE1 -> Power_IR, RE2 -> CS_MCP, RE3 -> LED_blue, RE4 -> power_sw1, RE5 -> Set to 1 for cR hardware |
| 448 | 102 clrf TRISE |
| 604 | 103 movlw b'00110001' ; init port |
| 0 | 104 movwf PORTE |
| 105 | |
| 604 | 106 movlw b'01111110' ; 1= input, (RF1, RF2, RF3, RF4, RF5) -> Analog |
| 0 | 107 movwf TRISF |
| 604 | 108 ; movlw b'00000000' ; init port |
| 448 | 109 clrf PORTF |
| 0 | 110 |
| 604 | 111 movlw b'00001110' ; 1= input, <7:6> not implemented, RG0 -> TX3_PIEZO_CFG, RG2 -> RX2, RG3 -> AN17_RSSI, RG4 -> SOSC_OUT, RG5 -> /RESET |
| 0 | 112 movwf TRISG |
| 604 | 113 movlw b'00000001' ; init port |
| 0 | 114 movwf PORTG |
| 115 | |
| 604 | 116 ; movlw b'00000000' ; 1= input -> Data TFT_low |
| 448 | 117 clrf TRISH |
| 604 | 118 ; movlw b'00000000' ; init port |
| 448 | 119 clrf PORTH |
| 0 | 120 |
| 604 | 121 movlw b'10011011' ; 1= input, RJ4 -> vusb_in, RJ5 -> power_sw2, RJ6 -> CLK_MS5541, RJ7 -> MISO_MS5541 |
| 0 | 122 movwf TRISJ |
| 604 | 123 movlw b'00100000' ; init port |
| 0 | 124 movwf PORTJ |
| 125 | |
| 126 | |
| 127 ; Timer 0 | |
| 604 | 128 movlw b'00000001' ; timer0 with 1:4 prescaler |
| 0 | 129 movwf T0CON |
| 130 | |
| 131 ; Timer 1 - Button hold-down timer | |
| 604 | 132 movlw b'10001100' ; 32768Hz clock source, 1:1 prescaler -> ; 30.51757813 µs/bit in TMR1L:TMR1H |
| 0 | 133 movwf T1CON |
| 134 | |
| 135 ; RTCC | |
| 608 | 136 banksel 0xF16 ; Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM. |
| 137 movlw 0x55 | |
| 138 movwf EECON2 | |
| 139 movlw 0xAA | |
| 140 movwf EECON2 | |
| 141 bsf RTCCFG,RTCWREN ; Unlock sequence for RTCWREN | |
| 0 | 142 bsf RTCCFG,RTCPTR1 |
| 143 bsf RTCCFG,RTCPTR0 | |
| 608 | 144 bsf RTCCFG,RTCEN ; Module enable |
| 145 bsf RTCCFG,RTCOE ; Output enable | |
| 146 movlw b'00000100' ; 32768Hz SOCS on RTCC pin (PORTG,4) Bit7-5: Pullups for Port D, E and J | |
| 0 | 147 movwf PADCFG1 |
| 148 movlw b'11000100' | |
| 149 movwf ALRMCFG ; 1 second alarm | |
| 150 movlw d'1' | |
| 608 | 151 movwf ALRMRPT ; Alarm repeat counter |
| 152 movlw 0x55 | |
| 153 movwf EECON2 | |
| 154 movlw 0xAA | |
| 155 movwf EECON2 | |
| 156 bcf RTCCFG,RTCWREN ; Lock sequence for RTCWREN | |
| 0 | 157 banksel common |
| 608 | 158 |
| 0 | 159 ; A/D Converter |
| 160 movlw b'00011000' ; power off ADC, select AN6 | |
| 161 movwf ADCON0 | |
| 162 movlw b'00100000' ; 2.048V Vref+ | |
| 163 movwf ADCON1 | |
| 604 | 164 movlw b'10001101' ; right aligned |
| 0 | 165 movwf ADCON2 |
| 166 | |
| 167 | |
| 604 | 168 ; init serial port1 (TRISC6/7) |
| 0 | 169 movlw b'00001000' ; BRG16=1 |
| 170 movwf BAUDCON1 | |
| 604 | 171 movlw .34 ; SPBRGH:SPBRG = .34 : 114285 BAUD @ 16MHz (+0.79% Error to 115200 BAUD) |
| 172 movwf SPBRG1 ; SPBRGH:SPBRG = .207 : 19230 BAUD @ 16MHz (-0.16% Error to 19200 BAUD) | |
| 0 | 173 clrf SPBRGH1 ; |
| 204 | 174 |
| 175 clrf RCSTA1 | |
| 604 | 176 clrf TXSTA1 ; UART disable |
| 177 bcf PORTC,6 ; TX hard to GND | |
| 0 | 178 |
| 604 | 179 ; init serial port2 (TRISG2) |
| 180 banksel BAUDCON2 | |
| 181 movlw b'00100000' ; BRG16=0 ; inverted for IR | |
| 0 | 182 movwf BAUDCON2 |
| 604 | 183 movlw b'00100000' ; BRGH=0, SYNC=0 |
| 184 movwf TXSTA2 | |
| 185 movlw .102 ; SPBRGH:SPBRG = .102 : 2403 BAUD @ 16MHz | |
| 186 movwf SPBRG2 | |
| 0 | 187 clrf SPBRGH2 |
| 604 | 188 movlw b'10010000' |
| 189 movwf RCSTA2 | |
| 190 banksel common | |
| 0 | 191 |
| 192 ; Timer3 for IR-RX Timeout | |
| 604 | 193 clrf T3GCON ; reset Timer3 gate control register |
| 194 movlw b'10001001' ; 1:1 prescaler -> 2 seconds@32768Hz, synced | |
| 0 | 195 ; 30,51757813µs/bit in TMR3L:TMR3H |
| 196 movwf T3CON | |
| 197 | |
| 198 ; SPI Module(s) | |
| 199 ; SPI2: External Flash | |
| 200 movlw b'00110000' | |
| 201 movwf SSP2CON1 | |
| 448 | 202 ; movlw b'00000000' |
| 203 clrf SSP2STAT | |
| 0 | 204 ; ->0,25MHz Bit clock @1MHz mode (Eco) |
| 205 ; -> 4MHz Bit clock @16MHz mode (Normal) | |
| 206 ; -> 16MHz Bit clock @64MHz mode (Fastest) | |
| 207 | |
| 208 ; MSSP1 Module: I2C Master | |
| 604 | 209 movlw b'00101000' ; I2C master mode |
| 0 | 210 movwf SSP1CON1 |
| 448 | 211 ; movlw b'00000000' |
| 212 clrf SSP1CON2 | |
| 0 | 213 movlw 0x27 |
| 604 | 214 movwf SSP1ADD ; 100kHz @ 16MHz Fosc |
| 0 | 215 |
| 216 ; PWM Module(s) | |
| 217 ; PWM1 for LED dimming | |
| 218 movlw b'00001100' | |
| 219 movwf CCP1CON | |
| 220 movlw b'00000001' | |
| 604 | 221 movwf PSTR1CON ; pulse steering disabled |
| 0 | 222 movlw d'255' |
| 604 | 223 movwf PR2 ; period |
| 224 ; 255 is max brightness (300 mW) | |
| 225 clrf CCPR1L ; duty cycle | |
| 226 clrf CCPR1H ; duty cycle | |
| 0 | 227 movlw T2CON_NORMAL |
| 228 movwf T2CON | |
| 229 | |
| 230 ; Timer5 for ISR-independent wait routines | |
| 604 | 231 clrf T5GCON ; reset Timer5 gate control register |
| 232 movlw b'10001001' ; 1:1 prescaler -> 2 seconds@32768Hz, synced | |
| 0 | 233 ; 30,51757813µs/bit in TMR5L:TMR5H |
| 234 movwf T5CON | |
| 235 | |
| 236 ; Timer7 for 62,5ms Interrupt (Sensor states) | |
| 604 | 237 banksel 0xF16 ; addresses, F16h through F5Fh, are also used by SFRs, but are not part of the access RAM |
| 238 clrf T7GCON ; reset Timer7 gate control register | |
| 239 movlw b'10001001' ; 1:1 prescaler -> 2 seconds@32768Hz, synced | |
| 0 | 240 movwf T7CON |
| 241 clrf TMR7L | |
| 242 movlw .248 | |
| 243 movwf TMR7H ; -> Rollover after 2048 cycles -> 62,5ms | |
| 244 | |
| 608 | 245 ; Turn off unused timer |
| 246 movlw b'11000000' | |
| 247 movwf PMD0 | |
| 248 movlw b'11010001' | |
| 249 movwf PMD1 | |
| 250 movlw b'11010111' | |
| 251 movwf PMD2 | |
| 252 movlw b'11111111' | |
| 253 movwf PMD3 | |
| 254 | |
| 255 ; CTMU | |
| 256 clrf CTMUCONH | |
| 257 clrf CTMUCONL | |
| 258 clrf CTMUICON | |
| 604 | 259 banksel common |
| 608 | 260 |
| 0 | 261 ; Interrupts |
| 50 | 262 movlw b'11010000' |
| 0 | 263 movwf INTCON |
| 604 | 264 movlw b'00001000' ; BIT7=1: pullup for PORTB disabled |
| 0 | 265 movwf INTCON2 |
|
77
131e6dd9e201
BUGFIX: Potential bug to freeze the OSTC3 after battery change or update
heinrichsweikamp
parents:
58
diff
changeset
|
266 movlw b'00000000' |
| 0 | 267 movwf INTCON3 |
| 268 movlw b'00000001' ; Bit0: TMR1 | |
| 269 movwf PIE1 | |
| 270 movlw b'00000010' ; Bit1: TMR3 | |
| 604 | 271 movwf PIE2 |
| 0 | 272 movlw b'00000000' ; Bit1: TMR5 |
| 273 movwf PIE5 | |
| 274 movlw b'00100001' ; Bit0: RTCC, Bit5: UART2 | |
| 275 movwf PIE3 | |
| 276 movlw b'00001000' ; Bit3: TMR7 | |
| 277 movwf PIE5 | |
| 278 | |
| 604 | 279 bsf power_sw1 |
| 280 btfss power_sw1 | |
| 281 bra $-4 | |
| 282 bsf power_sw2 | |
| 283 btfss power_sw2 | |
| 284 bra $-4 | |
| 0 | 285 |
| 604 | 286 bcf active_reset_ostc_rx ; start RX from RESET |
| 204 | 287 |
| 0 | 288 return |
| 289 | |
| 290 ;============================================================================= | |
| 291 global speed_eco | |
| 292 speed_eco: | |
| 293 movlw d'1' | |
| 608 | 294 movff WREG,cpu_speed_request ; bank-independent |
| 0 | 295 ; Done in ISR |
| 296 return | |
| 297 ;============================================================================= | |
| 298 global speed_normal | |
| 299 speed_normal: | |
| 300 movlw d'2' | |
| 608 | 301 movff WREG,cpu_speed_request ; bank-independent |
| 0 | 302 ; Done in ISR |
| 303 return | |
| 304 ;============================================================================= | |
| 305 global speed_fastest | |
| 306 speed_fastest: | |
| 307 movlw d'3' | |
| 608 | 308 movff WREG,cpu_speed_request ; bank-independent |
| 0 | 309 ; Done in ISR |
| 310 return | |
| 311 ;============================================================================= | |
| 312 | |
| 604 | 313 END |