Mercurial > public > hwos_code
annotate src/ostc3.asm @ 187:669b5d00706d
CHANGE: Longer timeout (4 min) for calibration menu
Ignore 1,2mV noise for not-connected inputs
| author | heinrichsweikamp |
|---|---|
| date | Sat, 25 Oct 2014 15:28:18 +0200 |
| parents | a004b482604a |
| children | 800f09c9089c |
| rev | line source |
|---|---|
| 0 | 1 ;============================================================================= |
| 2 ; | |
| 3 ; File ostc3.asm | |
| 4 ; | |
| 5 ; Definition of the ostc3 dive computer platform. | |
| 6 ; | |
| 7 ; Copyright (c) 2011, JD Gascuel, HeinrichsWeikamp, all right reserved. | |
| 8 ;============================================================================= | |
| 9 ; HISTORY | |
| 10 ; 2011-05-24 : [jDG] Cleanups from initial Matthias code. | |
| 11 ; 2011-06-24 : [MH] Added clock speeds. | |
| 12 #include "ostc3.inc" | |
| 13 | |
| 14 ;============================================================================= | |
| 15 ;----------------------------- CONFIG --------------------------------- | |
| 1 | 16 CONFIG RETEN = OFF ;Disabled - Controlled by SRETEN bit |
| 17 CONFIG SOSCSEL = HIGH ;High Power SOSC circuit selected | |
| 18 CONFIG XINST = OFF ;Code won't excute in extended mode... | |
| 19 CONFIG FOSC = INTIO2 ;Internal RC oscillator, no clock-out | |
| 20 CONFIG PLLCFG = OFF | |
| 21 CONFIG IESO = OFF ;Disabled | |
| 22 CONFIG PWRTEN = OFF ;Disabled, because incompatible with ICD3 (Ri-400) | |
| 23 CONFIG BOREN = ON ;Controlled with SBOREN bit | |
| 24 CONFIG BORV = 2 ;2.0V | |
| 25 CONFIG BORPWR = MEDIUM ;BORMV set to medium power level | |
| 26 CONFIG WDTEN = ON ;WDT controlled by SWDTEN bit setting | |
| 27 CONFIG WDTPS = 128 ;1:128 | |
| 28 CONFIG RTCOSC = SOSCREF ;RTCC uses SOSC | |
| 29 CONFIG MCLRE = ON ;MCLR Enabled, RG5 Disabled | |
| 30 CONFIG CCP2MX = PORTBE ;RE7-Microcontroller Mode/RB3-All other modes | |
| 0 | 31 ;============================================================================= |
| 32 boot CODE | |
| 33 global init_ostc3 | |
| 34 | |
| 35 init_ostc3: | |
| 36 banksel common ; Bank1 | |
| 37 ;init oscillator | |
| 38 movlw b'01110010' | |
| 39 movwf OSCCON ; 16MHz INTOSC | |
| 40 movlw b'00001000' | |
| 41 movwf OSCCON2 ; Secondary Oscillator running | |
| 42 movlw b'00000000' | |
| 43 movwf OSCTUNE ; 4x PLL Disable (Bit6) - only works with 8 or 16MHz (=32 or 64MHz) | |
| 44 bcf RCON,SBOREN ; Bown-Out off | |
| 45 bcf RCON,IPEN ; Priority Interrupts off | |
| 46 | |
| 47 ; I/O Ports | |
| 48 banksel 0xF16 ; Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM. | |
| 49 | |
| 50 clrf REFOCON ; No reference oscillator active on REFO pin | |
| 51 clrf ODCON1 ; Disable Open Drain capability | |
| 52 clrf ODCON2 ; Disable Open Drain capability | |
| 53 clrf ODCON3 ; Disable Open Drain capability | |
| 54 | |
| 55 movlw b'11000000' ; ANSEL, AN7 and AN6 -> Analog inputs, PORTA is digital. | |
| 56 movwf ANCON0 | |
| 113 | 57 movlw b'00000111' ; ANSEL, AN8, AN9, AN10 -> Analog in |
| 0 | 58 movwf ANCON1 |
| 59 movlw b'00000010' ; ANSEL, AN17 -> Analog input | |
| 60 movwf ANCON2 | |
| 61 | |
| 62 banksel common | |
| 63 | |
| 64 movlw b'00000000' ; 1= Input -> Data TFT_high | |
| 65 movwf TRISA | |
| 66 movlw b'00000000' ; Init port | |
| 67 movwf PORTA | |
| 68 | |
| 113 | 69 movlw b'00000011' ; 1= Input, (RB0, RB1) -> Switches, RB2 -> Power_MCP, RB3 -> s8_npower, RB4 -> LED_green, RB5 -> /TFT_POWER |
| 0 | 70 movwf TRISB |
| 113 | 71 movlw b'00101000' ; Init port |
| 0 | 72 movwf PORTB |
| 73 | |
| 74 movlw b'10011010' ; 1= Input, (RC0, RC1) -> SOSC, RC2 -> TFT_LED_PWM, (RC3,RC4) -> I²C, RC5 -> MOSI_MS5541, (RC6, RC7) -> UART1 | |
| 75 movwf TRISC | |
| 76 movlw b'00000000' ; Init port | |
| 77 movwf PORTC | |
| 78 | |
| 79 movlw b'00100000' ; 1= Input, RD0 -> TFT_NCS, RD1 -> TFT_RS, RD2 -> TFT_NWR, RD3 -> TFT_RD, RD4 -> MOSI_Flash, RD5 -> MISO_Flash, RD6 -> CLK_Flash, RD7 -> TFT_NRESET | |
| 80 movwf TRISD | |
| 81 movlw b'00000000' ; Init port | |
| 82 movwf PORTD | |
| 83 | |
| 186 | 84 movlw b'00000000' ; 1= Input, RE1 -> Power_IR, RE2 -> CS_MCP, RE3 -> LED_blue, RE4 -> power_sw1, RE5 -> Set to 1 for C3 hardware |
| 0 | 85 movwf TRISE |
| 186 | 86 movlw b'00110000' ; Init port |
| 0 | 87 movwf PORTE |
| 88 | |
| 113 | 89 movlw b'00111110' ; 1= Input, (RF1, RF2, RF3, RF4, RF5) -> Analog |
| 0 | 90 movwf TRISF |
| 91 movlw b'00000000' ; Init port | |
| 92 movwf PORTF | |
| 93 | |
| 113 | 94 movlw b'00001110' ; 1= Input, <7:6> not implemented, RG0 -> TX3_PIEZO_CFG, RG2 -> RX2, RG3 -> AN17_RSSI, RG4 -> SOSC_OUT, RG5 -> /RESET |
| 0 | 95 movwf TRISG |
| 113 | 96 movlw b'00000001' ; Init port |
| 0 | 97 movwf PORTG |
| 98 | |
| 99 movlw b'00000000' ; 1= Input -> Data TFT_low | |
| 100 movwf TRISH | |
| 101 movlw b'00000000' ; Init port | |
| 102 movwf PORTH | |
| 103 | |
| 120 | 104 movlw b'10011011' ; 1= Input, RJ4 -> vusb_in, RJ5 -> power_sw2, RJ6 -> CLK_MS5541, RJ7 -> MISO_MS5541 |
| 0 | 105 movwf TRISJ |
| 106 movlw b'00100000' ; Init port | |
| 107 movwf PORTJ | |
| 108 | |
| 109 | |
| 110 ; Timer 0 | |
| 28 | 111 movlw b'00000001' ; Timer0 with 1:4 prescaler |
| 112 ; movlw b'00001000' ; Timer0 with 1:1 prescaler | |
| 0 | 113 movwf T0CON |
| 114 | |
| 115 ; Timer 1 - Button hold-down timer | |
| 116 movlw b'10001100' ; 32768Hz clock source, 1:1 Prescaler -> ; 30,51757813µs/bit in TMR1L:TMR1H | |
| 117 movwf T1CON | |
| 118 | |
| 119 banksel 0xF16 ; Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM. | |
| 120 | |
| 121 ; RTCC | |
| 122 movlw 0x55 | |
| 123 movwf EECON2 | |
| 124 movlw 0xAA | |
| 125 movwf EECON2 | |
| 126 bsf RTCCFG,RTCWREN ; Unlock sequence for RTCWREN | |
| 127 bsf RTCCFG,RTCPTR1 | |
| 128 bsf RTCCFG,RTCPTR0 | |
| 129 bsf RTCCFG,RTCEN ; Module enable | |
| 130 bsf RTCCFG,RTCOE ; Output enable | |
| 131 movlw b'00000100' ; 32768Hz SOCS on RTCC pin (PORTG,4) Bit7-5: Pullups for Port D, E and J | |
| 132 movwf PADCFG1 | |
| 133 movlw b'11000100' | |
| 134 movwf ALRMCFG ; 1 second alarm | |
| 135 movlw d'1' | |
| 136 movwf ALRMRPT ; Alarm repeat counter | |
| 137 movlw 0x55 | |
| 138 movwf EECON2 | |
| 139 movlw 0xAA | |
| 140 movwf EECON2 | |
| 141 bcf RTCCFG,RTCWREN ; Lock sequence for RTCWREN | |
| 142 | |
| 143 banksel common | |
| 144 ; A/D Converter | |
| 145 movlw b'00011000' ; power off ADC, select AN6 | |
| 146 movwf ADCON0 | |
| 147 movlw b'00100000' ; 2.048V Vref+ | |
| 148 movwf ADCON1 | |
| 149 movlw b'10001101' ; Right justified | |
| 150 movwf ADCON2 | |
| 151 | |
| 152 | |
| 153 ;init serial port1 (TRISC6/7) | |
| 154 movlw b'00001000' ; BRG16=1 | |
| 155 movwf BAUDCON1 | |
| 156 movlw b'00100100' ; BRGH=1, SYNC=0 | |
| 157 movwf TXSTA1 | |
| 158 movlw .34 ; SPBRGH:SPBRG = .34 : 114285 BAUD @ 16MHz (+0,79% Error to 115200 BAUD) | |
| 159 movwf SPBRG1 ; SPBRGH:SPBRG = .207 : 19230 BAUD @ 16MHz (-0,16% Error to 19200 BAUD) | |
| 160 clrf SPBRGH1 ; | |
| 161 movlw b'10010000' | |
| 162 movwf RCSTA1 | |
| 163 | |
| 164 ;init serial port2 (TRISG2) | |
| 165 banksel BAUDCON2 | |
| 113 | 166 movlw b'00100000' ; BRG16=0 ; inverted for IR |
| 0 | 167 movwf BAUDCON2 |
| 168 movlw b'00100000' ; BRGH=0, SYNC=0 | |
| 169 movwf TXSTA2 | |
| 170 movlw .102 ; SPBRGH:SPBRG = .102 : 2403 BAUD @ 16MHz | |
| 171 movwf SPBRG2 | |
| 172 clrf SPBRGH2 | |
| 173 movlw b'10010000' | |
| 174 movwf RCSTA2 | |
| 175 banksel common | |
| 176 | |
| 177 ; Timer3 for IR-RX Timeout | |
| 178 clrf T3GCON ; Reset Timer3 Gate Control register | |
| 179 ; movlw b'10001101' ; 1:1 Prescaler -> 2seconds@32768Hz, not synced | |
| 180 movlw b'10001001' ; 1:1 Prescaler -> 2seconds@32768Hz, synced | |
| 181 ; 30,51757813µs/bit in TMR3L:TMR3H | |
| 182 movwf T3CON | |
| 183 | |
| 184 ; SPI Module(s) | |
| 185 ; SPI2: External Flash | |
| 186 movlw b'00110000' | |
| 187 movwf SSP2CON1 | |
| 188 movlw b'00000000' | |
| 189 movwf SSP2STAT | |
| 190 ; ->0,25MHz Bit clock @1MHz mode (Eco) | |
| 191 ; -> 4MHz Bit clock @16MHz mode (Normal) | |
| 192 ; -> 16MHz Bit clock @64MHz mode (Fastest) | |
| 193 | |
| 194 ; MSSP1 Module: I2C Master | |
| 195 movlw b'00101000' ; I2C Master Mode | |
| 196 movwf SSP1CON1 | |
| 197 movlw b'00000000' | |
| 198 movwf SSP1CON2 | |
| 199 movlw 0x27 | |
| 200 movwf SSP1ADD ; 100kHz @ 16MHz Fosc | |
| 201 | |
| 202 ; PWM Module(s) | |
| 203 ; PWM1 for LED dimming | |
| 204 movlw b'00001100' | |
| 205 movwf CCP1CON | |
| 206 movlw b'00000001' | |
| 207 movwf PSTR1CON ; Pulse steering disabled | |
| 208 movlw d'255' | |
| 209 movwf PR2 ; Period | |
| 210 ; 255 is max brightness (300mW) | |
| 211 clrf CCPR1L ; Duty cycle | |
| 212 clrf CCPR1H ; Duty cycle | |
| 213 movlw T2CON_NORMAL | |
| 214 movwf T2CON | |
| 215 | |
| 216 ; Timer5 for ISR-independent wait routines | |
| 217 clrf T5GCON ; Reset Timer5 Gate Control register | |
| 218 ; movlw b'10001101' ; 1:1 Prescaler -> 2seconds@32768Hz, not synced | |
| 219 movlw b'10001001' ; 1:1 Prescaler -> 2seconds@32768Hz, synced | |
| 220 ; 30,51757813µs/bit in TMR5L:TMR5H | |
| 221 movwf T5CON | |
| 222 | |
| 223 ; Timer7 for 62,5ms Interrupt (Sensor states) | |
| 224 banksel 0xF16 ; Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM. | |
| 225 clrf T7GCON ; Reset Timer7 Gate Control register | |
| 226 ; movlw b'10001101' ; 1:1 Prescaler -> 2seconds@32768Hz, not synced | |
| 227 movlw b'10001001' ; 1:1 Prescaler -> 2seconds@32768Hz, synced | |
| 228 movwf T7CON | |
| 229 clrf TMR7L | |
| 230 movlw .248 | |
| 231 movwf TMR7H ; -> Rollover after 2048 cycles -> 62,5ms | |
| 232 | |
| 233 banksel common | |
| 234 ; Interrupts | |
| 50 | 235 movlw b'11010000' |
| 0 | 236 movwf INTCON |
|
77
131e6dd9e201
BUGFIX: Potential bug to freeze the OSTC3 after battery change or update
heinrichsweikamp
parents:
58
diff
changeset
|
237 movlw b'00001000' ; BIT7=1: Pullup for PORTB disabled |
| 0 | 238 movwf INTCON2 |
|
77
131e6dd9e201
BUGFIX: Potential bug to freeze the OSTC3 after battery change or update
heinrichsweikamp
parents:
58
diff
changeset
|
239 movlw b'00000000' |
| 0 | 240 movwf INTCON3 |
| 241 movlw b'00000001' ; Bit0: TMR1 | |
| 242 movwf PIE1 | |
| 243 movlw b'00000010' ; Bit1: TMR3 | |
| 244 movwf PIE2 | |
| 245 movlw b'00000000' ; Bit1: TMR5 | |
| 246 movwf PIE5 | |
| 247 movlw b'00100001' ; Bit0: RTCC, Bit5: UART2 | |
| 248 movwf PIE3 | |
| 249 movlw b'00001000' ; Bit3: TMR7 | |
| 250 movwf PIE5 | |
| 251 | |
| 252 bsf power_sw1 | |
| 58 | 253 btfss power_sw1 |
| 254 bra $-4 | |
| 0 | 255 bsf power_sw2 |
| 58 | 256 btfss power_sw2 |
| 257 bra $-4 | |
| 0 | 258 |
| 259 return | |
| 260 | |
| 261 ;============================================================================= | |
| 262 global speed_eco | |
| 263 speed_eco: | |
| 264 movlw d'1' | |
| 265 movff WREG,speed_setting ; Bank-independent | |
| 266 ; Done in ISR | |
| 267 return | |
| 268 ;============================================================================= | |
| 269 global speed_normal | |
| 270 speed_normal: | |
| 271 movlw d'2' | |
| 272 movff WREG,speed_setting ; Bank-independent | |
| 273 ; Done in ISR | |
| 274 return | |
| 275 ;============================================================================= | |
| 276 global speed_fastest | |
| 277 speed_fastest: | |
| 278 movlw d'3' | |
| 279 movff WREG,speed_setting ; Bank-independent | |
| 280 ; Done in ISR | |
| 281 return | |
| 282 ;============================================================================= | |
| 283 | |
| 284 END |