Mercurial > public > hwos_code
annotate src/ostc3.asm @ 205:618191753d2b
Preparations for 1.7
author | heinrichsweikamp |
---|---|
date | Wed, 26 Nov 2014 14:30:25 +0100 |
parents | 93085f540746 |
children | 56276a2418f9 |
rev | line source |
---|---|
0 | 1 ;============================================================================= |
2 ; | |
3 ; File ostc3.asm | |
4 ; | |
5 ; Definition of the ostc3 dive computer platform. | |
6 ; | |
7 ; Copyright (c) 2011, JD Gascuel, HeinrichsWeikamp, all right reserved. | |
8 ;============================================================================= | |
9 ; HISTORY | |
10 ; 2011-05-24 : [jDG] Cleanups from initial Matthias code. | |
11 ; 2011-06-24 : [MH] Added clock speeds. | |
12 #include "ostc3.inc" | |
13 | |
14 ;============================================================================= | |
15 ;----------------------------- CONFIG --------------------------------- | |
1 | 16 CONFIG RETEN = OFF ;Disabled - Controlled by SRETEN bit |
17 CONFIG SOSCSEL = HIGH ;High Power SOSC circuit selected | |
199 | 18 CONFIG XINST = OFF ;Code won't excute in extended mode... |
1 | 19 CONFIG FOSC = INTIO2 ;Internal RC oscillator, no clock-out |
20 CONFIG PLLCFG = OFF | |
21 CONFIG IESO = OFF ;Disabled | |
22 CONFIG PWRTEN = OFF ;Disabled, because incompatible with ICD3 (Ri-400) | |
23 CONFIG BOREN = ON ;Controlled with SBOREN bit | |
24 CONFIG BORV = 2 ;2.0V | |
25 CONFIG BORPWR = MEDIUM ;BORMV set to medium power level | |
26 CONFIG WDTEN = ON ;WDT controlled by SWDTEN bit setting | |
27 CONFIG WDTPS = 128 ;1:128 | |
28 CONFIG RTCOSC = SOSCREF ;RTCC uses SOSC | |
29 CONFIG MCLRE = ON ;MCLR Enabled, RG5 Disabled | |
30 CONFIG CCP2MX = PORTBE ;RE7-Microcontroller Mode/RB3-All other modes | |
0 | 31 ;============================================================================= |
32 boot CODE | |
33 global init_ostc3 | |
34 | |
35 init_ostc3: | |
36 banksel common ; Bank1 | |
37 ;init oscillator | |
38 movlw b'01110010' | |
39 movwf OSCCON ; 16MHz INTOSC | |
40 movlw b'00001000' | |
41 movwf OSCCON2 ; Secondary Oscillator running | |
42 movlw b'00000000' | |
43 movwf OSCTUNE ; 4x PLL Disable (Bit6) - only works with 8 or 16MHz (=32 or 64MHz) | |
44 bcf RCON,SBOREN ; Bown-Out off | |
45 bcf RCON,IPEN ; Priority Interrupts off | |
199 | 46 banksel WDTCON |
47 movlw b'10000000' | |
48 movwf WDTCON ; Setup Watchdog | |
0 | 49 |
50 ; I/O Ports | |
51 banksel 0xF16 ; Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM. | |
52 | |
53 clrf REFOCON ; No reference oscillator active on REFO pin | |
54 clrf ODCON1 ; Disable Open Drain capability | |
55 clrf ODCON2 ; Disable Open Drain capability | |
56 clrf ODCON3 ; Disable Open Drain capability | |
57 | |
58 movlw b'11000000' ; ANSEL, AN7 and AN6 -> Analog inputs, PORTA is digital. | |
59 movwf ANCON0 | |
113 | 60 movlw b'00000111' ; ANSEL, AN8, AN9, AN10 -> Analog in |
0 | 61 movwf ANCON1 |
62 movlw b'00000010' ; ANSEL, AN17 -> Analog input | |
63 movwf ANCON2 | |
64 | |
65 banksel common | |
66 | |
67 movlw b'00000000' ; 1= Input -> Data TFT_high | |
68 movwf TRISA | |
69 movlw b'00000000' ; Init port | |
70 movwf PORTA | |
71 | |
113 | 72 movlw b'00000011' ; 1= Input, (RB0, RB1) -> Switches, RB2 -> Power_MCP, RB3 -> s8_npower, RB4 -> LED_green, RB5 -> /TFT_POWER |
0 | 73 movwf TRISB |
113 | 74 movlw b'00101000' ; Init port |
0 | 75 movwf PORTB |
76 | |
77 movlw b'10011010' ; 1= Input, (RC0, RC1) -> SOSC, RC2 -> TFT_LED_PWM, (RC3,RC4) -> I²C, RC5 -> MOSI_MS5541, (RC6, RC7) -> UART1 | |
78 movwf TRISC | |
79 movlw b'00000000' ; Init port | |
80 movwf PORTC | |
81 | |
82 movlw b'00100000' ; 1= Input, RD0 -> TFT_NCS, RD1 -> TFT_RS, RD2 -> TFT_NWR, RD3 -> TFT_RD, RD4 -> MOSI_Flash, RD5 -> MISO_Flash, RD6 -> CLK_Flash, RD7 -> TFT_NRESET | |
83 movwf TRISD | |
84 movlw b'00000000' ; Init port | |
85 movwf PORTD | |
86 | |
200 | 87 movlw b'00000000' ; 1= Input, RE1 -> Power_IR, RE2 -> CS_MCP, RE3 -> LED_blue, RE4 -> power_sw1, RE5 -> Set to 1 for cR hardware |
0 | 88 movwf TRISE |
186 | 89 movlw b'00110000' ; Init port |
0 | 90 movwf PORTE |
91 | |
113 | 92 movlw b'00111110' ; 1= Input, (RF1, RF2, RF3, RF4, RF5) -> Analog |
0 | 93 movwf TRISF |
94 movlw b'00000000' ; Init port | |
95 movwf PORTF | |
96 | |
113 | 97 movlw b'00001110' ; 1= Input, <7:6> not implemented, RG0 -> TX3_PIEZO_CFG, RG2 -> RX2, RG3 -> AN17_RSSI, RG4 -> SOSC_OUT, RG5 -> /RESET |
0 | 98 movwf TRISG |
113 | 99 movlw b'00000001' ; Init port |
0 | 100 movwf PORTG |
101 | |
102 movlw b'00000000' ; 1= Input -> Data TFT_low | |
103 movwf TRISH | |
104 movlw b'00000000' ; Init port | |
105 movwf PORTH | |
106 | |
120 | 107 movlw b'10011011' ; 1= Input, RJ4 -> vusb_in, RJ5 -> power_sw2, RJ6 -> CLK_MS5541, RJ7 -> MISO_MS5541 |
0 | 108 movwf TRISJ |
109 movlw b'00100000' ; Init port | |
110 movwf PORTJ | |
111 | |
112 | |
113 ; Timer 0 | |
28 | 114 movlw b'00000001' ; Timer0 with 1:4 prescaler |
115 ; movlw b'00001000' ; Timer0 with 1:1 prescaler | |
0 | 116 movwf T0CON |
117 | |
118 ; Timer 1 - Button hold-down timer | |
119 movlw b'10001100' ; 32768Hz clock source, 1:1 Prescaler -> ; 30,51757813µs/bit in TMR1L:TMR1H | |
120 movwf T1CON | |
121 | |
122 banksel 0xF16 ; Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM. | |
123 | |
124 ; RTCC | |
125 movlw 0x55 | |
126 movwf EECON2 | |
127 movlw 0xAA | |
128 movwf EECON2 | |
129 bsf RTCCFG,RTCWREN ; Unlock sequence for RTCWREN | |
130 bsf RTCCFG,RTCPTR1 | |
131 bsf RTCCFG,RTCPTR0 | |
132 bsf RTCCFG,RTCEN ; Module enable | |
133 bsf RTCCFG,RTCOE ; Output enable | |
134 movlw b'00000100' ; 32768Hz SOCS on RTCC pin (PORTG,4) Bit7-5: Pullups for Port D, E and J | |
135 movwf PADCFG1 | |
136 movlw b'11000100' | |
137 movwf ALRMCFG ; 1 second alarm | |
138 movlw d'1' | |
139 movwf ALRMRPT ; Alarm repeat counter | |
140 movlw 0x55 | |
141 movwf EECON2 | |
142 movlw 0xAA | |
143 movwf EECON2 | |
144 bcf RTCCFG,RTCWREN ; Lock sequence for RTCWREN | |
145 | |
146 banksel common | |
147 ; A/D Converter | |
148 movlw b'00011000' ; power off ADC, select AN6 | |
149 movwf ADCON0 | |
150 movlw b'00100000' ; 2.048V Vref+ | |
151 movwf ADCON1 | |
152 movlw b'10001101' ; Right justified | |
153 movwf ADCON2 | |
154 | |
155 | |
156 ;init serial port1 (TRISC6/7) | |
157 movlw b'00001000' ; BRG16=1 | |
158 movwf BAUDCON1 | |
204 | 159 ; movlw b'00100100' ; BRGH=1, SYNC=0 |
160 ; movwf TXSTA1 | |
0 | 161 movlw .34 ; SPBRGH:SPBRG = .34 : 114285 BAUD @ 16MHz (+0,79% Error to 115200 BAUD) |
162 movwf SPBRG1 ; SPBRGH:SPBRG = .207 : 19230 BAUD @ 16MHz (-0,16% Error to 19200 BAUD) | |
163 clrf SPBRGH1 ; | |
204 | 164 ; movlw b'10010000' |
165 ; movwf RCSTA1 | |
166 | |
167 clrf RCSTA1 | |
168 clrf TXSTA1 ; UART disable | |
169 bcf PORTC,6 ; TX hard to GND | |
0 | 170 |
171 ;init serial port2 (TRISG2) | |
172 banksel BAUDCON2 | |
113 | 173 movlw b'00100000' ; BRG16=0 ; inverted for IR |
0 | 174 movwf BAUDCON2 |
175 movlw b'00100000' ; BRGH=0, SYNC=0 | |
176 movwf TXSTA2 | |
177 movlw .102 ; SPBRGH:SPBRG = .102 : 2403 BAUD @ 16MHz | |
178 movwf SPBRG2 | |
179 clrf SPBRGH2 | |
180 movlw b'10010000' | |
181 movwf RCSTA2 | |
182 banksel common | |
183 | |
184 ; Timer3 for IR-RX Timeout | |
185 clrf T3GCON ; Reset Timer3 Gate Control register | |
186 ; movlw b'10001101' ; 1:1 Prescaler -> 2seconds@32768Hz, not synced | |
187 movlw b'10001001' ; 1:1 Prescaler -> 2seconds@32768Hz, synced | |
188 ; 30,51757813µs/bit in TMR3L:TMR3H | |
189 movwf T3CON | |
190 | |
191 ; SPI Module(s) | |
192 ; SPI2: External Flash | |
193 movlw b'00110000' | |
194 movwf SSP2CON1 | |
195 movlw b'00000000' | |
196 movwf SSP2STAT | |
197 ; ->0,25MHz Bit clock @1MHz mode (Eco) | |
198 ; -> 4MHz Bit clock @16MHz mode (Normal) | |
199 ; -> 16MHz Bit clock @64MHz mode (Fastest) | |
200 | |
201 ; MSSP1 Module: I2C Master | |
202 movlw b'00101000' ; I2C Master Mode | |
203 movwf SSP1CON1 | |
204 movlw b'00000000' | |
205 movwf SSP1CON2 | |
206 movlw 0x27 | |
207 movwf SSP1ADD ; 100kHz @ 16MHz Fosc | |
208 | |
209 ; PWM Module(s) | |
210 ; PWM1 for LED dimming | |
211 movlw b'00001100' | |
212 movwf CCP1CON | |
213 movlw b'00000001' | |
214 movwf PSTR1CON ; Pulse steering disabled | |
215 movlw d'255' | |
216 movwf PR2 ; Period | |
217 ; 255 is max brightness (300mW) | |
218 clrf CCPR1L ; Duty cycle | |
219 clrf CCPR1H ; Duty cycle | |
220 movlw T2CON_NORMAL | |
221 movwf T2CON | |
222 | |
223 ; Timer5 for ISR-independent wait routines | |
224 clrf T5GCON ; Reset Timer5 Gate Control register | |
225 ; movlw b'10001101' ; 1:1 Prescaler -> 2seconds@32768Hz, not synced | |
226 movlw b'10001001' ; 1:1 Prescaler -> 2seconds@32768Hz, synced | |
227 ; 30,51757813µs/bit in TMR5L:TMR5H | |
228 movwf T5CON | |
229 | |
230 ; Timer7 for 62,5ms Interrupt (Sensor states) | |
231 banksel 0xF16 ; Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM. | |
232 clrf T7GCON ; Reset Timer7 Gate Control register | |
233 ; movlw b'10001101' ; 1:1 Prescaler -> 2seconds@32768Hz, not synced | |
234 movlw b'10001001' ; 1:1 Prescaler -> 2seconds@32768Hz, synced | |
235 movwf T7CON | |
236 clrf TMR7L | |
237 movlw .248 | |
238 movwf TMR7H ; -> Rollover after 2048 cycles -> 62,5ms | |
239 | |
240 banksel common | |
241 ; Interrupts | |
50 | 242 movlw b'11010000' |
0 | 243 movwf INTCON |
77
131e6dd9e201
BUGFIX: Potential bug to freeze the OSTC3 after battery change or update
heinrichsweikamp
parents:
58
diff
changeset
|
244 movlw b'00001000' ; BIT7=1: Pullup for PORTB disabled |
0 | 245 movwf INTCON2 |
77
131e6dd9e201
BUGFIX: Potential bug to freeze the OSTC3 after battery change or update
heinrichsweikamp
parents:
58
diff
changeset
|
246 movlw b'00000000' |
0 | 247 movwf INTCON3 |
248 movlw b'00000001' ; Bit0: TMR1 | |
249 movwf PIE1 | |
250 movlw b'00000010' ; Bit1: TMR3 | |
251 movwf PIE2 | |
252 movlw b'00000000' ; Bit1: TMR5 | |
253 movwf PIE5 | |
254 movlw b'00100001' ; Bit0: RTCC, Bit5: UART2 | |
255 movwf PIE3 | |
256 movlw b'00001000' ; Bit3: TMR7 | |
257 movwf PIE5 | |
258 | |
259 bsf power_sw1 | |
58 | 260 btfss power_sw1 |
261 bra $-4 | |
0 | 262 bsf power_sw2 |
58 | 263 btfss power_sw2 |
264 bra $-4 | |
0 | 265 |
204 | 266 movlw d'2' |
267 movwf speed_setting ; Normal | |
268 | |
269 | |
0 | 270 return |
271 | |
272 ;============================================================================= | |
273 global speed_eco | |
274 speed_eco: | |
275 movlw d'1' | |
276 movff WREG,speed_setting ; Bank-independent | |
277 ; Done in ISR | |
278 return | |
279 ;============================================================================= | |
280 global speed_normal | |
281 speed_normal: | |
282 movlw d'2' | |
283 movff WREG,speed_setting ; Bank-independent | |
284 ; Done in ISR | |
285 return | |
286 ;============================================================================= | |
287 global speed_fastest | |
288 speed_fastest: | |
289 movlw d'3' | |
290 movff WREG,speed_setting ; Bank-independent | |
291 ; Done in ISR | |
292 return | |
293 ;============================================================================= | |
294 | |
295 END |