Mercurial > public > hwos_code
annotate src/rtc.asm @ 547:49be7b31b4db
2.25 stable RC2
author | heinrichsweikamp |
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date | Fri, 08 Sep 2017 13:36:04 +0200 (2017-09-08) |
parents | 8dfb93e80338 |
children | b7eb98dbd800 |
rev | line source |
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0 | 1 ;============================================================================= |
2 ; | |
3 ; File rtc.asm | |
4 ; | |
5 ; | |
6 ; Copyright (c) 2011, JD Gascuel, HeinrichsWeikamp, all right reserved. | |
7 ;============================================================================= | |
8 ; HISTORY | |
9 ; 2011-08-08 : [mH] moving from OSTC code | |
10 | |
275 | 11 #include "hwos.inc" |
0 | 12 #include "math.inc" |
13 | |
14 sensors CODE | |
15 | |
16 global rtc_init | |
17 rtc_init: | |
18 movlw .1 | |
19 movwf secs | |
20 movlw .59 | |
21 movwf mins | |
22 movlw .12 | |
23 movwf hours | |
490
8dfb93e80338
NEW: Deep Sleep mode for OSTC Plus and OSTC 2 (2017) (Entered automatically)
heinrichsweikamp
parents:
463
diff
changeset
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24 movlw .29 |
0 | 25 movwf day |
265 | 26 movlw .3 |
0 | 27 movwf month |
490
8dfb93e80338
NEW: Deep Sleep mode for OSTC Plus and OSTC 2 (2017) (Entered automatically)
heinrichsweikamp
parents:
463
diff
changeset
|
28 movlw .17 |
0 | 29 movwf year |
463 | 30 ; rcall rtc_set_rtc ; writes mins,sec,hours,day,month and year to rtc module |
31 ; return | |
0 | 32 |
33 global rtc_set_rtc | |
34 rtc_set_rtc: | |
35 banksel 0xF16 ; Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM. | |
36 movlw 0x55 | |
37 movwf EECON2 | |
38 movlw 0xAA | |
39 movwf EECON2 | |
40 bsf RTCCFG,RTCWREN ; Unlock sequence for RTCWREN | |
41 bsf RTCCFG,RTCPTR1 | |
42 bsf RTCCFG,RTCPTR0 ; year | |
43 movff year,WREG | |
44 rcall rtc_dec2bcd ; IN: temp1 in WREG, OUT: WREG in BCD, also sets to bank16h! | |
45 movwf RTCVALL ; year | |
46 movwf RTCVALH ; dummy write | |
47 movff day,WREG | |
48 rcall rtc_dec2bcd ; IN: temp1 in WREG, OUT: WREG in BCD, also sets to bank16h! | |
49 movwf RTCVALL ;day | |
50 movff month,WREG | |
51 rcall rtc_dec2bcd ; IN: temp1 in WREG, OUT: WREG in BCD, also sets to bank16h! | |
52 movwf RTCVALH ;month | |
53 movff hours,WREG | |
54 rcall rtc_dec2bcd ; IN: temp1 in WREG, OUT: WREG in BCD, also sets to bank16h! | |
55 movwf RTCVALL ;hours | |
56 movlw d'0' | |
57 rcall rtc_dec2bcd ; IN: temp1 in WREG, OUT: WREG in BCD, also sets to bank16h! | |
58 movwf RTCVALH ;weekday | |
59 movff secs,WREG | |
60 rcall rtc_dec2bcd ; IN: temp1 in WREG, OUT: WREG in BCD, also sets to bank16h! | |
61 movwf RTCVALL ;secs | |
62 movff mins,WREG | |
63 rcall rtc_dec2bcd ; IN: temp1 in WREG, OUT: WREG in BCD, also sets to bank16h! | |
64 movwf RTCVALH ;minutes | |
65 movlw 0x55 | |
66 movwf EECON2 | |
67 movlw 0xAA | |
68 movwf EECON2 | |
69 bcf RTCCFG,RTCWREN ; Lock sequence for RTCWREN | |
70 banksel common | |
71 return | |
72 | |
73 rtc_dec2bcd: | |
74 banksel temp1 | |
75 movwf temp1 ; Input in dec | |
76 setf temp2 ; 10s | |
77 | |
78 rtc_dec2bcd2: | |
79 incf temp2,F ; Count 10's | |
80 movlw d'10' | |
81 subwf temp1,F | |
82 btfss STATUS,N | |
83 bra rtc_dec2bcd2 | |
84 movlw d'10' | |
85 addwf temp1,F ; 1s | |
86 swapf temp2,W ; swap to bit 7-4 -> WREG | |
87 addwf temp1,W ; Result in BCD | |
88 banksel 0xF16 ; Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM. | |
89 return | |
90 | |
91 END |