annotate src/external_flash.asm @ 586:06642f6ffe59

2.97 release
author heinrichsweikamp
date Thu, 01 Mar 2018 11:12:47 +0100
parents b455b31ce022
children ca4556fb60b9
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
0
heinrichsweikamp
parents:
diff changeset
1 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
2 ;
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
3 ; File external_flash.asm ## V2.98
0
heinrichsweikamp
parents:
diff changeset
4 ;
heinrichsweikamp
parents:
diff changeset
5 ; External flash
heinrichsweikamp
parents:
diff changeset
6 ;
heinrichsweikamp
parents:
diff changeset
7 ; Copyright (c) 2011, JD Gascuel, HeinrichsWeikamp, all right reserved.
heinrichsweikamp
parents:
diff changeset
8 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
9 ; HISTORY
heinrichsweikamp
parents:
diff changeset
10 ; 2011-08-12 : [mH] creation
heinrichsweikamp
parents:
diff changeset
11
275
653a3ab08062 rename into hwOS
heinrichsweikamp
parents: 167
diff changeset
12 #include "hwos.inc"
0
heinrichsweikamp
parents:
diff changeset
13 #include "wait.inc"
heinrichsweikamp
parents:
diff changeset
14
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
15 basic CODE
0
heinrichsweikamp
parents:
diff changeset
16 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
17
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
18 global incf_ext_flash_address_p1
0
heinrichsweikamp
parents:
diff changeset
19 incf_ext_flash_address_p1: ; Increase by one
heinrichsweikamp
parents:
diff changeset
20 movlw .1
heinrichsweikamp
parents:
diff changeset
21
heinrichsweikamp
parents:
diff changeset
22 global incf_ext_flash_address0
heinrichsweikamp
parents:
diff changeset
23 incf_ext_flash_address0:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
24 addwf ext_flash_address+0,F ; increase address
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
25 movlw d'0'
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
26 addwfc ext_flash_address+1,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
27 addwfc ext_flash_address+2,F
0
heinrichsweikamp
parents:
diff changeset
28
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
29 movlw 0x40
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
30 cpfseq ext_flash_address+2 ; at address 40FFFF?
0
heinrichsweikamp
parents:
diff changeset
31 return ; No, return
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
32 ; clrf ext_flash_address+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
33 ; clrf ext_flash_address+1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
34 clrf ext_flash_address+2 ; Yes, rollover to 0x000000
0
heinrichsweikamp
parents:
diff changeset
35 return
heinrichsweikamp
parents:
diff changeset
36
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
37
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
38 global incf_ext_flash_address0_p1_0x20
0
heinrichsweikamp
parents:
diff changeset
39 incf_ext_flash_address0_p1_0x20: ; Increase by one
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
40 movlw .1
0
heinrichsweikamp
parents:
diff changeset
41
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
42 global incf_ext_flash_address0_0x20
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
43 incf_ext_flash_address0_0x20: ; with roll-over at 0x200000 to 0x000000
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
44 addwf ext_flash_address+0,F ; increase address
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
45 movlw d'0'
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
46 addwfc ext_flash_address+1,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
47 addwfc ext_flash_address+2,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
48 movlw 0x20
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
49 cpfseq ext_flash_address+2 ; at address 0x200000?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
50 return ; No, return
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
51 ; clrf ext_flash_address+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
52 ; clrf ext_flash_address+1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
53 clrf ext_flash_address+2 ; Yes, rollover to 0x000000
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
54 return
0
heinrichsweikamp
parents:
diff changeset
55
heinrichsweikamp
parents:
diff changeset
56
heinrichsweikamp
parents:
diff changeset
57 global decf_ext_flash_address0
heinrichsweikamp
parents:
diff changeset
58 decf_ext_flash_address0:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
59 subwf ext_flash_address+0,F ; decrease address: do a 16-8bits subtract
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
60 movlw d'0'
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
61 subwfb ext_flash_address+1,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
62 movlw d'0'
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
63 subwfb ext_flash_address+2,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
64 btfss ext_flash_address+2,7 ; Rollover to 0xFFFFFF?
0
heinrichsweikamp
parents:
diff changeset
65 return ; No, return
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
66 clrf ext_flash_address+2 ; Set to 0x00FFFFF
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
67 setf ext_flash_address+1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
68 setf ext_flash_address+0
0
heinrichsweikamp
parents:
diff changeset
69 return
heinrichsweikamp
parents:
diff changeset
70
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
71
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
72 global ext_flash_byte_read_plus ; Return data read in WREG and SSP2BUF and
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
73 ext_flash_byte_read_plus: ; increase address after read
0
heinrichsweikamp
parents:
diff changeset
74 rcall ext_flash_byte_read
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
75 movwf ext_flash_rw ; store received data
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
76 bra incf_ext_flash_address_p1 ; +1 and return
0
heinrichsweikamp
parents:
diff changeset
77
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
78
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
79 global ext_flash_byte_read_plus_0x20 ; Return data read in WREG and SSP2BUF and
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
80 ext_flash_byte_read_plus_0x20: ; increase address after read with banking at 0x200000
0
heinrichsweikamp
parents:
diff changeset
81 rcall ext_flash_byte_read
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
82 movwf ext_flash_rw ; store received data
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
83 bra incf_ext_flash_address0_p1_0x20 ;+1 and return
0
heinrichsweikamp
parents:
diff changeset
84
heinrichsweikamp
parents:
diff changeset
85
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
86 global ext_flash_byte_read ; Return data read in WREG
0
heinrichsweikamp
parents:
diff changeset
87 ext_flash_byte_read:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
88 movlw 0x03 ; Read command
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
89 rcall write_spi
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
90 rcall ext_flash_write_address ; Write 24bit address ext_flash_address:3 via SPI
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
91 rcall write_spi ; Dummy write to read data into WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
92 bsf flash_ncs ; CS=1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
93 movwf ext_flash_rw
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
94 return ; Return data read in WREG and ext_flash_rw
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
95
0
heinrichsweikamp
parents:
diff changeset
96
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
97 ext_flash_write_address: ; Write 24bit address ext_flash_address:3 via SPI
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
98 movf ext_flash_address+2,W ; 24Bit Address
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
99 rcall write_spi
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
100 movf ext_flash_address+1,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
101 rcall write_spi
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
102 movf ext_flash_address+0,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
103 bra write_spi ; And return....
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
104
0
heinrichsweikamp
parents:
diff changeset
105
heinrichsweikamp
parents:
diff changeset
106 global ext_flash_read_block_start ; Return data read in WREG
heinrichsweikamp
parents:
diff changeset
107 ext_flash_read_block_start:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
108 movlw 0x03 ; Read command
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
109 rcall write_spi
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
110 rcall ext_flash_write_address ; Write 24bit address ext_flash_address:3 via SPI
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
111 rcall write_spi ; Dummy write to read data into WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
112 return ; Return data read in WREG
0
heinrichsweikamp
parents:
diff changeset
113
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
114
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
115 global ext_flash_read_block ; Return data read in WREG
0
heinrichsweikamp
parents:
diff changeset
116 ext_flash_read_block:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
117 rcall incf_ext_flash_address_p1 ; Increase address +1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
118 bra write_spi1 ; Dummy write to read data into WREG and return
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
119
0
heinrichsweikamp
parents:
diff changeset
120
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
121 global ext_flash_read_block_stop ; Return data read in WREG
0
heinrichsweikamp
parents:
diff changeset
122 ext_flash_read_block_stop:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
123 bsf flash_ncs ; CS=1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
124 return ; NO data in WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
125
0
heinrichsweikamp
parents:
diff changeset
126
heinrichsweikamp
parents:
diff changeset
127 global write_byte_ext_flash_plus_header
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
128 write_byte_ext_flash_plus_header: ; Write from WREG and increase address after write
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
129 movwf ext_flash_rw ; store data
0
heinrichsweikamp
parents:
diff changeset
130 ; test if write is done at first byte of 4kB block
heinrichsweikamp
parents:
diff changeset
131 ; if yes -> delete 4kB block first
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
132 tstfsz ext_flash_address+0 ; at 0x00?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
133 bra write_byte_ext_flash_plus_h1 ; No, normal Write
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
134 movf ext_flash_address+1,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
135 andlw 0x0F ; Mask lower nibble
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
136 tstfsz WREG ; at 0x.0?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
137 bra write_byte_ext_flash_plus_h1 ; No, normal Write
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
138 ; At beginning of 4kB block -> erase first!
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
139 rcall ext_flash_erase4kB ; Erases 4kB sector @ext_flash_address:3
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
140 write_byte_ext_flash_plus_h1:
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
141 movf ext_flash_rw,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
142 rcall ext_flash_byte_write ; Write the byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
143 bra incf_ext_flash_address_p1 ; +1 and return
0
heinrichsweikamp
parents:
diff changeset
144
heinrichsweikamp
parents:
diff changeset
145
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
146 global write_byte_ext_flash_plus_nocnt ; No increase of ext_flash_dive_counter:3
279
62c7af4795b0 bugfix wrong profile length in header
heinrichsweikamp
parents: 278
diff changeset
147 write_byte_ext_flash_plus_nocnt:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
148 movwf ext_flash_rw ; store data
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
149 bra write_byte_ext_flash_plus2
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
150
279
62c7af4795b0 bugfix wrong profile length in header
heinrichsweikamp
parents: 278
diff changeset
151
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
152 global write_byte_ext_flash_plus_nodel ; Does NOT delete 4kB Page when required
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
153 write_byte_ext_flash_plus_nodel: ; Write from WREG and increase address after write with banking at 0x200000
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
154 movwf ext_flash_rw ; store data
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
155 bra write_byte_ext_flash_plus1 ; Ignore possible begin of 4kB page, there have been written 0xFF already
6
13cda523891f bugfix: dive length in normal header
heinrichsweikamp
parents: 0
diff changeset
156
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
157 global write_byte_ext_flash_plus ; Write from WREG and increase address after write with banking at 0x200000
0
heinrichsweikamp
parents:
diff changeset
158 write_byte_ext_flash_plus:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
159 movwf ext_flash_rw ; store data
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
160 ; First, increase dive length counter
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
161 incf ext_flash_dive_counter+0,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
162 movlw .0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
163 addwfc ext_flash_dive_counter+1,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
164 addwfc ext_flash_dive_counter+2,F ; 24bit++
0
heinrichsweikamp
parents:
diff changeset
165
6
13cda523891f bugfix: dive length in normal header
heinrichsweikamp
parents: 0
diff changeset
166 write_byte_ext_flash_plus2:
0
heinrichsweikamp
parents:
diff changeset
167 ; Now test if write is done at first byte of 4kB block
heinrichsweikamp
parents:
diff changeset
168 ; if yes -> delete 4kB block first
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
169 tstfsz ext_flash_address+0 ; at 0x00?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
170 bra write_byte_ext_flash_plus1 ; No, normal Write
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
171 movf ext_flash_address+1,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
172 andlw 0x0F ; Mask lower nibble
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
173 tstfsz WREG ; at 0x.0?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
174 bra write_byte_ext_flash_plus1 ; No, normal Write
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
175 ; At beginning of 4kB block -> erase first!
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
176 rcall ext_flash_erase4kB ; Erases 4kB sector @ext_flash_address:3
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
177 write_byte_ext_flash_plus1:
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
178 movf ext_flash_rw,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
179 rcall ext_flash_byte_write ; Write the byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
180 bra incf_ext_flash_address0_p1_0x20 ; +1 and roll over at 0x200000 to 0x000000 and return
0
heinrichsweikamp
parents:
diff changeset
181
heinrichsweikamp
parents:
diff changeset
182
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
183 global ext_flash_byte_write ; Write from WREG
0
heinrichsweikamp
parents:
diff changeset
184 ext_flash_byte_write:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
185 movwf ext_flash_rw ; store data byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
186 bsf flash_ncs ; CS=1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
187 movlw 0x06 ; WREN command
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
188 rcall write_spi
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
189 bsf flash_ncs ; CS=1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
190 movlw 0x02 ; Write (PP, Page-Program) command
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
191 rcall write_spi
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
192 rcall ext_flash_write_address ; Write 24bit address ext_flash_address:3 via SPI
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
193 movf ext_flash_rw,W ; load data byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
194 rcall write_spi ; write one byte of data!
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
195 bra ext_flash_wait_write ; And return...
423
ccaaac45b61a _another_ timing fix for firmware updates (2.07 was not published yet anyway)
heinrichsweikamp
parents: 421
diff changeset
196
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
197
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
198 global ext_flash_byte_write_comms ; without wait, ~86us fixed delay due to 115200 Bauds
423
ccaaac45b61a _another_ timing fix for firmware updates (2.07 was not published yet anyway)
heinrichsweikamp
parents: 421
diff changeset
199 ext_flash_byte_write_comms:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
200 movwf ext_flash_rw ; store data byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
201 bsf flash_ncs ; CS=1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
202 movlw 0x06 ; WREN command
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
203 rcall write_spi
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
204 bsf flash_ncs ; CS=1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
205 movlw 0x02 ; Write (PP, Page-Program) command
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
206 rcall write_spi
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
207 rcall ext_flash_write_address ; Write 24bit address ext_flash_address:3 via SPI
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
208 movf ext_flash_rw,W ; load data byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
209 rcall write_spi ; write one byte of data!
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
210 bsf flash_ncs ; CS=1
423
ccaaac45b61a _another_ timing fix for firmware updates (2.07 was not published yet anyway)
heinrichsweikamp
parents: 421
diff changeset
211 return
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
212
0
heinrichsweikamp
parents:
diff changeset
213
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
214 global ext_flash_disable_protection ; Disable write protection
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
215 ext_flash_disable_protection:
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
216 ; unlock old memory
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
217 bsf flash_ncs ; CS=1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
218 movlw 0x50 ; EWSR command
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
219 rcall write_spi
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
220 bsf flash_ncs ; CS=1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
221 movlw 0x01 ; WRSR command
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
222 rcall write_spi
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
223 movlw b'00000000' ; New status
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
224 rcall write_spi
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
225 bsf flash_ncs ; CS=1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
226 ; unlock new memory
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
227 movlw 0x06 ; WREN command
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
228 rcall write_spi
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
229 bsf flash_ncs ; CS=1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
230 movlw 0x98 ; ULBPR command
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
231 rcall write_spi
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
232 bsf flash_ncs ; CS=1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
233 movlw 0x06 ; WREN command
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
234 rcall write_spi
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
235 bsf flash_ncs ; CS=1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
236 movlw 0x42 ; WBPR command
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
237 rcall write_spi
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
238 movlw .18
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
239 movwf lo
420
789230298511 fix handling for new flash memory chip
heinrichsweikamp
parents: 416
diff changeset
240 ext_flash_disable_protection2:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
241 movlw 0x00
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
242 rcall write_spi
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
243 decfsz lo,F ; 18 bytes with 0x00
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
244 bra ext_flash_disable_protection2
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
245 bsf flash_ncs ; CS=1
0
heinrichsweikamp
parents:
diff changeset
246 return
heinrichsweikamp
parents:
diff changeset
247
heinrichsweikamp
parents:
diff changeset
248 global ext_flash_enable_protection
heinrichsweikamp
parents:
diff changeset
249 ext_flash_enable_protection:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
250 ; lock old memory
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
251 bsf flash_ncs ; CS=1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
252 movlw 0x50 ; EWSR command
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
253 rcall write_spi
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
254 bsf flash_ncs ; CS=1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
255 movlw 0x01 ; WRSR command
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
256 rcall write_spi
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
257 movlw b'00011100' ; New status (Write protect on)
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
258 rcall write_spi
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
259 bsf flash_ncs ; CS=1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
260 ; lock new memory
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
261 ; movlw 0x06 ; WREN command
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
262 ; rcall write_spi
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
263 ; bsf flash_ncs ; CS=1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
264 ; movlw 0x8D ; LBPR command
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
265 ; rcall write_spi
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
266 ; bsf flash_ncs ; CS=1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
267 movlw 0x06 ; WREN command
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
268 rcall write_spi
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
269 bsf flash_ncs ; CS=1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
270 movlw 0x42 ; WBPR command
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
271 rcall write_spi
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
272 movlw .18
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
273 movwf lo
414
35bdfd89323c support for new flash memory
heinrichsweikamp
parents: 281
diff changeset
274 ext_flash_enable_protection2:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
275 movlw 0xFF
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
276 rcall write_spi
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
277 decfsz lo,F ; 18 bytes with 0xFF
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
278 bra ext_flash_enable_protection2
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
279 bsf flash_ncs ; CS=1
0
heinrichsweikamp
parents:
diff changeset
280 return
heinrichsweikamp
parents:
diff changeset
281
heinrichsweikamp
parents:
diff changeset
282
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
283 global ext_flash_erase4kB ; Erases 4kB sector
0
heinrichsweikamp
parents:
diff changeset
284 ext_flash_erase4kB:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
285 bsf flash_ncs ; CS=1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
286 movlw 0x06 ; WREN command
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
287 rcall write_spi
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
288 bsf flash_ncs ; CS=1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
289 movlw 0x20 ; Sector erase command
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
290 rcall write_spi
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
291 rcall ext_flash_write_address ; Write 24bit address ext_flash_address:3 via SPI
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
292 ; bra ext_flash_wait_write ; Wait for write... and return
0
heinrichsweikamp
parents:
diff changeset
293 ext_flash_wait_write:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
294 bsf flash_ncs ; CS=1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
295 ; WAITMS d'1' ; TBE/TSE=25ms...
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
296 movlw 0x05 ; RDSR command
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
297 rcall write_spi ; Read status
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
298 rcall write_spi ; Read status into WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
299 bsf flash_ncs ; CS=1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
300 btfsc SSP2BUF,0 ; Write operation in process?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
301 bra ext_flash_wait_write ; Yes, wait more..
0
heinrichsweikamp
parents:
diff changeset
302 return
heinrichsweikamp
parents:
diff changeset
303
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
304
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
305 global ext_flash_erase_logbook ; erases logbook memory (000000h -> 2FFFFFh -> 3MByte -> 3145728 Bytes)
0
heinrichsweikamp
parents:
diff changeset
306 ext_flash_erase_logbook:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
307 bsf flash_ncs ; CS=1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
308 clrf ext_flash_address+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
309 clrf ext_flash_address+1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
310 clrf ext_flash_address+2
0
heinrichsweikamp
parents:
diff changeset
311
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
312 setf ext_flash_rw ; 256*12kB=3145728 Bytes
0
heinrichsweikamp
parents:
diff changeset
313 ext_flash_erase_logbook_loop:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
314 rcall ext_flash_erase4kB ; 4kB
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
315 rcall ext_flash_add_4kB ; Increase ext_flash_address:3 by 4kB
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
316 rcall ext_flash_erase4kB ; 4kB
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
317 rcall ext_flash_add_4kB ; Increase ext_flash_address:3 by 4kB
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
318 rcall ext_flash_erase4kB ; 4kB
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
319 rcall ext_flash_add_4kB ; Increase ext_flash_address:3 by 4kB
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
320 decfsz ext_flash_rw,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
321 bra ext_flash_erase_logbook_loop
0
heinrichsweikamp
parents:
diff changeset
322 return
heinrichsweikamp
parents:
diff changeset
323
414
35bdfd89323c support for new flash memory
heinrichsweikamp
parents: 281
diff changeset
324 ext_flash_add_4kB:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
325 movlw 0x10
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
326 addwf ext_flash_address+1,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
327 movlw d'0'
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
328 addwfc ext_flash_address+2,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
329 return
414
35bdfd89323c support for new flash memory
heinrichsweikamp
parents: 281
diff changeset
330
0
heinrichsweikamp
parents:
diff changeset
331
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
332 write_spi: ; With data in WREG...
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
333 bcf flash_ncs ; CS
0
heinrichsweikamp
parents:
diff changeset
334 global write_spi1
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
335 write_spi1: ; With data in WREG...
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
336 bcf SSP2STAT,WCOL ; Clear flag
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
337 movwf SSP2BUF ; Write to buffer
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
338 btfsc SSP2STAT,WCOL ; Was buffer full?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
339 bra write_spi1 ; Yes, try again
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
340 write_spi2: ; Wait for write command
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
341 btfss SSP2STAT, BF ; Buffer full?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
342 bra write_spi2 ; No, wait.
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
343 movf SSP2BUF,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
344 return ; Returns RX data in WREG and SSP2BUF
0
heinrichsweikamp
parents:
diff changeset
345
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 561
diff changeset
346 END