annotate src/isr.asm @ 592:05053910d668

BUGFIX: Re-enable Sensors after sleep in PSCR mode
author heinrichsweikamp
date Wed, 18 Apr 2018 17:03:52 +0200
parents b455b31ce022
children ca4556fb60b9
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1 ;=============================================================================
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2 ;
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3 ; File isr.asm REFACTORED VERSION V2.98
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4 ;
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5 ; INTERUPT subroutines
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6 ;
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7 ; Copyright (c) 2011, JD Gascuel, HeinrichsWeikamp, all right reserved.
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8 ;=============================================================================
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9 ; HISTORY
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10 ; 2011-05-24 : [jDG] Cleanups from initial Matthias code.
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11
275
653a3ab08062 rename into hwOS
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12 #include "hwos.inc"
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13 #include "shared_definitions.h" ; Mailbox from/to p2_deco.c
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14 #include "ms5541.inc"
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15 #include "adc_lightsensor.inc"
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16 #include "eeprom_rs232.inc"
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17
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18 ;=============================================================================
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19
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20 extern start
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21
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22 isr_high CODE 0x0008 ; High Priority Interrupts
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23 bra HighInt
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24 nop
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25 nop
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26 nop
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27 nop
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28 nop
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29 nop
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30 bra HighInt
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31
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32 isr_low CODE 0x00018 ; Low Priority Interrupts
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33 ; *** low priority interrupts not used
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34 retfie FAST ; Restores BSR, STATUS and WREG
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35
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36 HighInt:
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37 movff PRODL,isr_prod+0
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38 movff PRODH,isr_prod+1
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39
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40 ; Buttons
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41 btfsc PIR1,TMR1IF ; Timer1 INT (Button hold-down Timer)
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42 rcall timer1int
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43 btfsc INTCON,INT0IF ; Buttons
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44 rcall isr_switch_right
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45 btfsc INTCON3,INT1IF ; Buttons
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46 rcall isr_switch_left
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47
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48 ; IR/S8 link timer int
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49 btfsc PIR3,RC2IF ; UART2
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50 rcall isr_uart2 ; IR/S8-Link
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51 btfsc PIR2,TMR3IF ; Timer 3
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52 rcall isr_timer3 ; IR-Link Timeout
113
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53
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54 ; Pressure sensor and others
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55 btfsc PIR5,TMR7IF ; Timer 7
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56 rcall isr_tmr7 ; Every 62,5ms
113
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57
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58 ; RTCC
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59 btfsc PIR3,RTCCIF ; Real-time-clock interrupt
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60 rcall isr_rtcc ; May return in bank common!
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61
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62 movff isr_prod+1,PRODH
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63 movff isr_prod+0,PRODL
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64 retfie FAST ; Restores BSR, STATUS and WREG
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65
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66 isr_set_speed_to_normal:
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67 ; Set speed to normal
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68 movlw b'01110010'
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69 movwf OSCCON ; 16MHz INTOSC
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70 movlw b'00000000'
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71 movwf OSCTUNE ; 4x PLL Disable (Bit6) - only works with 8 or 16MHz (=32 or 64MHz)
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72 movlw b'00001101' ; 1:2 Postscaler, 1:4 Prescaler, Timer 2 start -> 1960Hz (no-flicker)
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73 movwf T2CON
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74 btfss OSCCON,HFIOFS
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75 bra $-2 ; Wait until clock is stable
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76 return
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77
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78 isr_dimm_tft: ; Adjust until max_CCPR1L=CCPR1L !
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79 banksel common
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80 btfsc tft_is_dimming ; Ignore while dimming
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81 return
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82 banksel isr_backup
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83 movf max_CCPR1L,W
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84 cpfsgt CCPR1L ; CCPR1L>max_CCPR1L?
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85 bra isr_dimm_tft2 ; No, dimm up
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86 ; dimm down
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87 decf CCPR1L,F ; -1
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88 return
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89 isr_dimm_tft2:
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90 movf max_CCPR1L,W
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91 sublw ambient_light_min_eco
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92 cpfsgt CCPR1L ; CCPR1L>max_CCPR1L-ambient_light_min_eco?
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93 bra isr_dimm_tft3 ; No, dimm up slow
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94 ; dimm up faster
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95 movlw .10
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96 addwf CCPR1L,F
410
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97 isr_dimm_tft3:
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98 incf CCPR1L,F ; +1
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99 return
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100 nop
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101 nop ; block flash here
410
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102
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103 isr_restore CODE 0x00080 ; Restore first flash page from EEPROM
410
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104 restore_flash_0x00080:
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105 goto restore_flash
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106
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107 isr_routines ; CODE
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108 ;=============================================================================
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109
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110 isr_uart2: ; IR/S8-Link
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111 banksel RCREG2
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112 movf RCREG2,W
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113 bcf RCSTA2,CREN ; Clear receiver status
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114 bsf RCSTA2,CREN
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115 banksel isr_backup
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116 incf ir_s8_counter,F ; Increase counter
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117 movff ir_s8_counter,isr1_temp ; Copy
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118 dcfsnz isr1_temp,F
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119 movwf ir_s8_buffer+.0
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120 dcfsnz isr1_temp,F
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121 movwf ir_s8_buffer+.1
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122 dcfsnz isr1_temp,F
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123 movwf ir_s8_buffer+.2
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124 dcfsnz isr1_temp,F
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125 movwf ir_s8_buffer+.3
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126 dcfsnz isr1_temp,F
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127 movwf ir_s8_buffer+.4
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128 dcfsnz isr1_temp,F
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129 movwf ir_s8_buffer+.5
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130 dcfsnz isr1_temp,F
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131 movwf ir_s8_buffer+.6
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132 dcfsnz isr1_temp,F
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133 movwf ir_s8_buffer+.7
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134 dcfsnz isr1_temp,F
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135 movwf ir_s8_buffer+.8
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136 dcfsnz isr1_temp,F
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137 movwf ir_s8_buffer+.9
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138 dcfsnz isr1_temp,F
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139 movwf ir_s8_buffer+.10
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140 dcfsnz isr1_temp,F
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141 movwf ir_s8_buffer+.11
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142 dcfsnz isr1_temp,F
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143 movwf ir_s8_buffer+.12
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144 dcfsnz isr1_temp,F
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145 movwf ir_s8_buffer+.13
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146 dcfsnz isr1_temp,F
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147 movwf ir_s8_buffer+.14
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148 dcfsnz isr1_temp,F
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149 movwf ir_s8_buffer+.15
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150 dcfsnz isr1_temp,F
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151 movwf ir_s8_buffer+.16
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152 dcfsnz isr1_temp,F
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153 movwf ir_s8_buffer+.17
113
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154
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155 clrf TMR3L ; Preload timer
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156 movlw .253
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157 movwf TMR3H
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158 bsf T3CON,TMR3ON ; (Re)Start Timeout counter
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159 return
0
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160
582
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161 isr_timer3: ; IR/S8-Link Timeout
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162 bcf T3CON,TMR3ON ; Stop Timer3
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163 banksel isr_backup ; Select Bank0 for ISR data.
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164 movlw .15
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165 cpfseq ir_s8_counter ; Got exact 15bytes?
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166 bra isr_timer3_1 ; No, test for 16bytes
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167 bra isr_timer3_ir ; Got 15 bytes, compute local checksum
0
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168 isr_timer3_1:
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169 movlw .16
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170 cpfseq ir_s8_counter ; Got exact 16bytes?
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parents: 570
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171 bra isr_timer3_2 ; No, test for 17bytes
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heinrichsweikamp
parents: 570
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172 tstfsz ir_s8_buffer+.15 ; Last byte=0x00
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parents: 570
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173 bra isr_timer3_exit ; No, exit
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174 bra isr_timer3_ir ; Got 16 bytes, compute local checksum
113
heinrichsweikamp
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175 isr_timer3_2:
582
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176 movlw .17
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177 cpfseq ir_s8_counter ; Got exact 17bytes?
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178 bra isr_timer3_exit ; No, exit
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179 bra isr_timer3_s8 ; S8 data
0
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180
582
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181 isr_timer3_ir: ; IR input
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182 movff ir_s8_buffer+.0,PRODL
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183 clrf PRODH
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184 movf ir_s8_buffer+.1,W
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185 rcall isr_timer3_checksum
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186 movf ir_s8_buffer+.2,W
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diff changeset
187 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
188 movf ir_s8_buffer+.3,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
189 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
190 movf ir_s8_buffer+.4,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
191 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
192 movf ir_s8_buffer+.5,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
193 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
194 movf ir_s8_buffer+.6,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
195 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
196 movf ir_s8_buffer+.7,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
197 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
198 movf ir_s8_buffer+.8,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
199 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
200 movf ir_s8_buffer+.9,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
201 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
202 movf ir_s8_buffer+.10,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
203 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
204 movf ir_s8_buffer+.11,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
205 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
206 movf ir_s8_buffer+.12,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
207 rcall isr_timer3_checksum
0
heinrichsweikamp
parents:
diff changeset
208
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
209 ; Compare checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
210 movf ir_s8_buffer+.13,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
211 cpfseq PRODL ; Checksum ok?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
212 bra isr_timer3_exit ; No, exit
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
213 movf ir_s8_buffer+.14,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
214 cpfseq PRODH ; Checksum ok?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
215 bra isr_timer3_exit ; No, exit
0
heinrichsweikamp
parents:
diff changeset
216
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
217 ; Checksum OK, copy results
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
218 movff ir_s8_buffer+.1,hud_status_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
219 movff ir_s8_buffer+.2,o2_mv_sensor1+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
220 movff ir_s8_buffer+.3,o2_mv_sensor1+1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
221 movff ir_s8_buffer+.4,o2_mv_sensor2+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
222 movff ir_s8_buffer+.5,o2_mv_sensor2+1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
223 movff ir_s8_buffer+.6,o2_mv_sensor3+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
224 movff ir_s8_buffer+.7,o2_mv_sensor3+1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
225 movff ir_s8_buffer+.8,o2_ppo2_sensor1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
226 movff ir_s8_buffer+.9,o2_ppo2_sensor2
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
227 movff ir_s8_buffer+.10,o2_ppo2_sensor3
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
228 movff ir_s8_buffer+.11,hud_battery_mv+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
229 movff ir_s8_buffer+.12,hud_battery_mv+1
0
heinrichsweikamp
parents:
diff changeset
230
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
231 movlw ir_timeout_value ; multiples of 62,5ms
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
232 movwf ir_s8_timeout ; Reload timeout
227
03946aa48fa5 NEW: Support for hwHUD without the LED module
heinrichsweikamp
parents: 204
diff changeset
233
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
234 banksel hud_status_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
235 bsf hud_connection_ok ; Set manually for hwHUD w/o the HUD module...
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
236 banksel isr_backup ; Select Bank0 for ISR data.
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
237
0
heinrichsweikamp
parents:
diff changeset
238 isr_timer3_exit:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
239 clrf ir_s8_counter ; Clear pointer
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
240 bcf PIR2,TMR3IF ; Clear flag
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
241 return
0
heinrichsweikamp
parents:
diff changeset
242
heinrichsweikamp
parents:
diff changeset
243 isr_timer3_checksum:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
244 addwf PRODL,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
245 movlw .0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
246 addwfc PRODH,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
247 return
0
heinrichsweikamp
parents:
diff changeset
248
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
249 isr_timer3_s8: ; S8 input
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
250 movff ir_s8_buffer+.0,PRODL
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
251 clrf PRODH
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
252 movf ir_s8_buffer+.1,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
253 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
254 movf ir_s8_buffer+.2,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
255 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
256 movf ir_s8_buffer+.3,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
257 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
258 movf ir_s8_buffer+.4,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
259 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
260 movf ir_s8_buffer+.5,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
261 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
262 movf ir_s8_buffer+.6,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
263 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
264 movf ir_s8_buffer+.7,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
265 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
266 movf ir_s8_buffer+.8,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
267 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
268 movf ir_s8_buffer+.9,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
269 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
270 movf ir_s8_buffer+.10,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
271 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
272 movf ir_s8_buffer+.11,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
273 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
274 movf ir_s8_buffer+.12,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
275 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
276 movf ir_s8_buffer+.13,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
277 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
278 movf ir_s8_buffer+.14,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
279 rcall isr_timer3_checksum
113
heinrichsweikamp
parents: 50
diff changeset
280
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
281 ; Compare checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
282 movf ir_s8_buffer+.15,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
283 cpfseq PRODL ; Checksum ok?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
284 bra isr_timer3_exit ; No, exit
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
285 movf ir_s8_buffer+.16,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
286 cpfseq PRODH ; Checksum ok?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
287 bra isr_timer3_exit ; No, exit
113
heinrichsweikamp
parents: 50
diff changeset
288
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
289 ; Checksum OK, copy results
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
290 movff ir_s8_buffer+.3,hud_status_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
291 movff ir_s8_buffer+.13,hud_battery_mv+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
292 movff ir_s8_buffer+.14,hud_battery_mv+1
113
heinrichsweikamp
parents: 50
diff changeset
293
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
294 banksel common
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
295 btfsc new_s8_data_available ; =1: Old data already processed?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
296 bra isr_timer3_skip ; No, skip copying new results
113
heinrichsweikamp
parents: 50
diff changeset
297
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
298 movff ir_s8_buffer+.6,s8_rawdata_sensor1+2
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
299 movff ir_s8_buffer+.5,s8_rawdata_sensor1+1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
300 movff ir_s8_buffer+.4,s8_rawdata_sensor1+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
301 movff ir_s8_buffer+.9,s8_rawdata_sensor2+2
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
302 movff ir_s8_buffer+.8,s8_rawdata_sensor2+1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
303 movff ir_s8_buffer+.7,s8_rawdata_sensor2+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
304 movff ir_s8_buffer+.12,s8_rawdata_sensor3+2
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
305 movff ir_s8_buffer+.11,s8_rawdata_sensor3+1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
306 movff ir_s8_buffer+.10,s8_rawdata_sensor3+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
307 banksel common
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
308 bsf new_s8_data_available ; set flag
268
29acdb601548 BUGFIX: Increase timing tolerance for S8 HUD (cR only)
heinrichsweikamp
parents: 236
diff changeset
309
29acdb601548 BUGFIX: Increase timing tolerance for S8 HUD (cR only)
heinrichsweikamp
parents: 236
diff changeset
310 isr_timer3_skip:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
311 banksel ir_s8_timeout
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
312 movlw ir_timeout_value ; multiples of 62,5ms
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
313 movwf ir_s8_timeout ; Reload timeout
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
314 bra isr_timer3_exit ; Exit
113
heinrichsweikamp
parents: 50
diff changeset
315
heinrichsweikamp
parents: 50
diff changeset
316
0
heinrichsweikamp
parents:
diff changeset
317 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
318
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
319 isr_tmr7: ; each 62,5ms
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
320 bcf PIR5,TMR7IF ; clear flag
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
321 banksel 0xF16 ; Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM.
469
heinrichsweikamp
parents: 453
diff changeset
322 movlw .248
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
323 movwf TMR7H ; -> Rollover after 2048 cycles -> 62,5ms
0
heinrichsweikamp
parents:
diff changeset
324
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
325 banksel common
448
aadfe9f2edaf work on new battery options
heinrichsweikamp
parents: 410
diff changeset
326 call get_analog_switches ; Get analog readings
aadfe9f2edaf work on new battery options
heinrichsweikamp
parents: 410
diff changeset
327 btfss INTCON3,INT1IE
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
328 bra isr_tmr7_a
448
aadfe9f2edaf work on new battery options
heinrichsweikamp
parents: 410
diff changeset
329 btfsc analog_sw2_pressed
aadfe9f2edaf work on new battery options
heinrichsweikamp
parents: 410
diff changeset
330 rcall isr_switch_left
aadfe9f2edaf work on new battery options
heinrichsweikamp
parents: 410
diff changeset
331 isr_tmr7_a:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
332 banksel common
448
aadfe9f2edaf work on new battery options
heinrichsweikamp
parents: 410
diff changeset
333 btfss INTCON,INT0IE
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
334 bra isr_tmr7_b
448
aadfe9f2edaf work on new battery options
heinrichsweikamp
parents: 410
diff changeset
335 btfsc analog_sw1_pressed
aadfe9f2edaf work on new battery options
heinrichsweikamp
parents: 410
diff changeset
336 rcall isr_switch_right
aadfe9f2edaf work on new battery options
heinrichsweikamp
parents: 410
diff changeset
337 isr_tmr7_b:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
338 banksel common
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
339 btfss no_sensor_int ; No sensor interrupt (because it's addressed during sleep)
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
340 bra isr_tmr7_c ; No, continue
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
341 banksel isr_backup ; Back to Bank0 ISR data
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
342 return
490
8dfb93e80338 NEW: Deep Sleep mode for OSTC Plus and OSTC 2 (2017) (Entered automatically)
heinrichsweikamp
parents: 469
diff changeset
343 isr_tmr7_c:
8dfb93e80338 NEW: Deep Sleep mode for OSTC Plus and OSTC 2 (2017) (Entered automatically)
heinrichsweikamp
parents: 469
diff changeset
344 banksel isr_backup
8dfb93e80338 NEW: Deep Sleep mode for OSTC Plus and OSTC 2 (2017) (Entered automatically)
heinrichsweikamp
parents: 469
diff changeset
345 movf max_CCPR1L,W ; Dimm value
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
346 cpfseq CCPR1L ; = current PWM value?
490
8dfb93e80338 NEW: Deep Sleep mode for OSTC Plus and OSTC 2 (2017) (Entered automatically)
heinrichsweikamp
parents: 469
diff changeset
347 rcall isr_dimm_tft ; No, adjust until max_CCPR1L=CCPR1L !
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
348
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
349 banksel isr_backup
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
350 decfsz ir_s8_timeout,F ; IR Data still valid?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
351 bra isr_tmr7_2 ; Yes, continue
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
352 ; timeout, clear IR-Data
0
heinrichsweikamp
parents:
diff changeset
353
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
354 movlw ir_timeout_value ; multiples of 62,5ms
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
355 movwf ir_s8_timeout ; Reload timeout
0
heinrichsweikamp
parents:
diff changeset
356
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
357 banksel common
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
358 btfss analog_o2_input
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
359 bra isr_tmr7_1a ; Always with normal ostc3 hardware
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
360 btfss s8_digital
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
361 bra isr_tmr7_2 ; only when digital
113
heinrichsweikamp
parents: 50
diff changeset
362 isr_tmr7_1a:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
363 clrf o2_mv_sensor1+0 ; S8/IR timeout clears all analog input readings to zero -> Fallback will be triggered when sensor mode was used
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
364 clrf o2_mv_sensor1+1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
365 clrf o2_mv_sensor2+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
366 clrf o2_mv_sensor2+1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
367 clrf o2_mv_sensor3+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
368 clrf o2_mv_sensor3+1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
369 banksel hud_battery_mv
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
370 clrf hud_battery_mv+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
371 clrf hud_battery_mv+1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
372 banksel hud_status_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
373 clrf hud_status_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
374 clrf o2_ppo2_sensor1 ; for IR/S8 UD
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
375 clrf o2_ppo2_sensor2
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
376 clrf o2_ppo2_sensor3
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
377
570
c8ea60294175 react to external S8 HUD disconnect or failure in surface mode
heinrichsweikamp
parents: 565
diff changeset
378 banksel common
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
379 bsf new_s8_data_available ; set flag to update in surface mode
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
380
0
heinrichsweikamp
parents:
diff changeset
381 isr_tmr7_2:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
382 banksel common
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
383 btfss no_sensor_int ; No sensor interrupt (because it's addressed during sleep)
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
384 bra isr_sensor_state2 ; No, continue
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
385 banksel isr_backup ; Back to Bank0 ISR data
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
386 return
0
heinrichsweikamp
parents:
diff changeset
387
heinrichsweikamp
parents:
diff changeset
388 isr_sensor_state2:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
389 banksel common
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
390 movff sensor_state_counter,WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
391 btfss WREG,0 ; every 1/4 second
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
392 bsf quarter_second_update ; Set flag
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
393 banksel isr_backup ; Back to Bank0 ISR data
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
394 movlw d'2'
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
395 cpfseq speed_setting ; Set to normal in case it's not already in normal speed mode
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
396 rcall isr_set_speed_to_normal
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
397
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
398 incf sensor_state_counter,F ; counts to eight for state machine
0
heinrichsweikamp
parents:
diff changeset
399
heinrichsweikamp
parents:
diff changeset
400 ; State 1: Clear flags and average registers, get temperature (51us) and start pressure integration (73,5us)
heinrichsweikamp
parents:
diff changeset
401 ; State 2: Get pressure (51us), start temperature integration (73,5us) and calculate temperature compensated pressure (233us)
heinrichsweikamp
parents:
diff changeset
402 ; State 3: Get temperature (51us) and start pressure integration (73,5us)
heinrichsweikamp
parents:
diff changeset
403 ; State 4: Get pressure (51us), start temperature integration (73,5us) and calculate temperature compensated pressure (233us)
heinrichsweikamp
parents:
diff changeset
404 ; State 5: Get temperature (51us) and start pressure integration (73,5us)
heinrichsweikamp
parents:
diff changeset
405 ; State 6: Get pressure (51us), start temperature integration (73,5us) and calculate temperature compensated pressure (233us)
heinrichsweikamp
parents:
diff changeset
406 ; State 7: Get temperature (51us) and start pressure integration (73,5us)
heinrichsweikamp
parents:
diff changeset
407 ; State 8: Get pressure (51us), start temperature integration (73,5us), calculate temperature compensated pressure (233us) and build average for half-second update of tempperature and pressure
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
408
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
409 movff sensor_state_counter,WREG ; WREG used as temp here...
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
410 dcfsnz WREG,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
411 bra sensor_int_state1_plus_restart ; Do State 1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
412 dcfsnz WREG,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
413 bra sensor_int_state2 ; Do State 2
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
414 dcfsnz WREG,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
415 bra sensor_int_state1 ; Do State 3
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
416 dcfsnz WREG,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
417 bra sensor_int_state2 ; Do State 4
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
418 dcfsnz WREG,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
419 bra sensor_int_state1 ; Do State 5
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
420 dcfsnz WREG,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
421 bra sensor_int_state2 ; Do State 6
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
422 dcfsnz WREG,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
423 bra sensor_int_state1 ; Do State 7
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
424 ; bra sensor_int2_plus_average ; Do State 8
0
heinrichsweikamp
parents:
diff changeset
425 ;sensor_int2_plus_average:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
426 ; First, do state2:
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
427 call get_pressure_value ; State2: Get pressure (51us)
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
428 call get_temperature_start ; and start temperature integration (73,5us)
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
429 call calculate_compensation ; calculate temperature compensated pressure (27us)
0
heinrichsweikamp
parents:
diff changeset
430 ; Build average
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
431 bcf STATUS,C ; clear carry bit.
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
432 rrcf amb_pressure_avg+1 ; amb_pressure sum / 2
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
433 rrcf amb_pressure_avg+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
434 bcf STATUS,C ; clear carry bit, twice.
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
435 rrcf amb_pressure_avg+1 ; amb_pressure sum / 4
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
436 rrcf amb_pressure_avg+0
0
heinrichsweikamp
parents:
diff changeset
437
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
438 movff amb_pressure_avg+1,amb_pressure+1 ; copy into actual register
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
439 movff amb_pressure_avg+0,amb_pressure+0
0
heinrichsweikamp
parents:
diff changeset
440
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
441 bcf STATUS,C
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
442 btfsc temperature_avg+1,7 ; Copy sign bit to carry
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
443 bsf STATUS,C
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
444 rrcf temperature_avg+1 ; Signed temperature /2
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
445 rrcf temperature_avg+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
446 bcf STATUS,C
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
447 btfsc temperature_avg+1,7 ; Copy sign bit to carry
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
448 bsf STATUS,C
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
449 rrcf temperature_avg+1 ; Signed temperature /4
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
450 rrcf temperature_avg+0
0
heinrichsweikamp
parents:
diff changeset
451
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
452 movff temperature_avg+1,temperature+1 ; copy into actual register
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
453 movff temperature_avg+0,temperature+0
0
heinrichsweikamp
parents:
diff changeset
454
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
455 banksel common ; flag1 is in Bank1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
456 bcf temp_changed ; Clear flag for temperature update
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
457 bcf pressure_refresh ; Clear flag for pressure update
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
458 banksel isr_backup ; Back to Bank0 ISR data
0
heinrichsweikamp
parents:
diff changeset
459
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
460 ; Temp changed?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
461 movf temperature+0,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
462 cpfseq last_temperature+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
463 bra isr_sensor_state2_2 ; Yes
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
464 movf temperature+1,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
465 cpfseq last_temperature+1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
466 bra isr_sensor_state2_2 ; Yes
0
heinrichsweikamp
parents:
diff changeset
467
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
468 bra isr_sensor_state2_3 ; no change
0
heinrichsweikamp
parents:
diff changeset
469
heinrichsweikamp
parents:
diff changeset
470 isr_sensor_state2_2:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
471 banksel common ; flag1 is in Bank1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
472 bsf temp_changed ; Yes
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
473 banksel isr_backup ; Back to Bank0 ISR data
0
heinrichsweikamp
parents:
diff changeset
474 isr_sensor_state2_3:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
475 movff temperature+0,last_temperature+0 ; Copy for compare
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
476 movff temperature+1,last_temperature+1
0
heinrichsweikamp
parents:
diff changeset
477
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
478 movf amb_pressure+0,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
479 cpfseq last_pressure+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
480 bra isr_sensor_state2_4 ; Yes
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
481 movf amb_pressure+1,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
482 cpfseq last_pressure+1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
483 bra isr_sensor_state2_4 ; Yes
0
heinrichsweikamp
parents:
diff changeset
484
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
485 bra isr_sensor_state2_5 ; No change
0
heinrichsweikamp
parents:
diff changeset
486 isr_sensor_state2_4:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
487 banksel common ; flag1 is in Bank1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
488 bsf pressure_refresh ; Yes
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
489 banksel isr_backup ; Back to Bank0 ISR data
0
heinrichsweikamp
parents:
diff changeset
490 isr_sensor_state2_5:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
491 movff amb_pressure+0,last_pressure+0 ; Copy for compare
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
492 movff amb_pressure+1,last_pressure+1
0
heinrichsweikamp
parents:
diff changeset
493
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
494 clrf sensor_state_counter ; Then reset State counter
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
495 banksel common ; flag2 is in Bank1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
496 btfss simulatormode_active ; are we in simulator mode?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
497 bra comp_air_pressure ; no
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
498 ; Always set pressure_refresh flag in simulator mode
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
499 bsf pressure_refresh ; Yes
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
500 banksel isr_backup ; Back to Bank0 ISR data
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
501 movlw LOW d'1000' ; yes, so simulate 1000mbar surface pressure
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
502 movwf last_surfpressure+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
503 movlw HIGH d'1000'
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
504 movwf last_surfpressure+1
0
heinrichsweikamp
parents:
diff changeset
505
heinrichsweikamp
parents:
diff changeset
506 comp_air_pressure:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
507 banksel isr_backup ; Back to Bank0 ISR data
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
508 movf last_surfpressure+0,W ; compensate air pressure
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
509 subwf amb_pressure+0,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
510 movwf rel_pressure+0 ; rel_pressure stores depth!
0
heinrichsweikamp
parents:
diff changeset
511
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
512 movf last_surfpressure+1,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
513 subwfb amb_pressure+1,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
514 movwf rel_pressure+1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
515 btfss STATUS,N ; result is below zero?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
516 bra sensor_int_state_exit
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
517 clrf rel_pressure+0 ; Yes, do not display negative depths
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
518 clrf rel_pressure+1 ; e.g. when surface air pressure dropped during the dive
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
519 bra sensor_int_state_exit
0
heinrichsweikamp
parents:
diff changeset
520
heinrichsweikamp
parents:
diff changeset
521 sensor_int_state1_plus_restart:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
522 clrf amb_pressure_avg+0 ; pressure average registers
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
523 clrf amb_pressure_avg+1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
524 clrf temperature_avg+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
525 clrf temperature_avg+1
0
heinrichsweikamp
parents:
diff changeset
526
heinrichsweikamp
parents:
diff changeset
527 sensor_int_state1:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
528 call get_temperature_value ; State 1: Get temperature
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
529 call get_pressure_start ; and start pressure integration.
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
530 bra sensor_int_state_exit
0
heinrichsweikamp
parents:
diff changeset
531
heinrichsweikamp
parents:
diff changeset
532 sensor_int_state2:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
533 call get_pressure_value ; State2: Get pressure (51us)
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
534 call get_temperature_start ; and start temperature integration (73,5us)
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
535 call calculate_compensation ; calculate temperature compensated pressure (233us)
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
536 ;bra sensor_int_state_exit
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
537
0
heinrichsweikamp
parents:
diff changeset
538 sensor_int_state_exit:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
539 rcall isr_restore_clock ; Restore clock
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
540 return
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
541
0
heinrichsweikamp
parents:
diff changeset
542 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
543
heinrichsweikamp
parents:
diff changeset
544 isr_rtcc: ; each second
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
545 bcf PIR3,RTCCIF ; clear flag
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
546 banksel 0xF16 ; Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM.
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
547 bsf RTCCFG,RTCPTR1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
548 bsf RTCCFG,RTCPTR0 ; year
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
549 movff RTCVALL,year ; format is BCD!
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
550 movff RTCVALH,day ; dummy read
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
551 movff RTCVALL,day ; format is BCD!
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
552 movff RTCVALH,month ; format is BCD!
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
553 movff RTCVALL,hours ; format is BCD!
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
554 movff RTCVALH,secs ; format is BCD!
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
555 movff RTCVALL,secs ; format is BCD!
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
556 movff RTCVALH,mins ; format is BCD!
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
557 banksel isr_backup ; Back to Bank0 ISR data
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
558
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
559 ; Convert BCD to DEC and set registers
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
560 movff mins, isr1_temp
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
561 rcall isr_rtcc_convert ; Converts to dec with result in WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
562 movff WREG,mins
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
563 movff secs, isr1_temp
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
564 rcall isr_rtcc_convert ; Converts to dec with result in WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
565 movff WREG,secs
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
566 movff hours, isr1_temp
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
567 rcall isr_rtcc_convert ; Converts to dec with result in WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
568 movff WREG,hours
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
569 movff month, isr1_temp
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
570 rcall isr_rtcc_convert ; Converts to dec with result in WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
571 movff WREG,month
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
572 movff day, isr1_temp
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
573 rcall isr_rtcc_convert ; Converts to dec with result in WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
574 movff WREG,day
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
575 movff year, isr1_temp
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
576 rcall isr_rtcc_convert ; Converts to dec with result in WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
577 movff WREG,year
0
heinrichsweikamp
parents:
diff changeset
578
heinrichsweikamp
parents:
diff changeset
579 ; Place once/second tasks for ISR here (Be sure of the right bank!)
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
580 banksel common ; flag1 is in Bank1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
581 btfss sleepmode ; in Sleepmode?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
582 call get_ambient_level ; No, get ambient light level and set max_CCPR1L
0
heinrichsweikamp
parents:
diff changeset
583
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
584 rcall isr_battery_gauge ; Add amount of battery consumption to battery_gauge:6
0
heinrichsweikamp
parents:
diff changeset
585
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
586 ; update uptime
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
587 banksel uptime+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
588 incf uptime+0,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
589 movlw .0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
590 addwfc uptime+1,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
591 addwfc uptime+2,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
592 addwfc uptime+3,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
593
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
594 banksel common ; flag1 is in Bank1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
595 bsf onesecupdate ; A new second has begun
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
596 btfsc divemode ; in divemode?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
597 rcall isr_divemode_1sec ; Yes, do some divemode stuff in bank common
0
heinrichsweikamp
parents:
diff changeset
598
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
599 btfss divemode ; in divemode?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
600 rcall isr_update_lastdive_time ; No, update the lastdive timer
453
b4f28ab23b87 NEW: Show Uptime (Time since last firmware boot) in information menu
heinrichsweikamp
parents: 451
diff changeset
601
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
602 tstfsz secs ; secs == 0 ?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
603 return ; No, Done.
0
heinrichsweikamp
parents:
diff changeset
604
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
605 bsf oneminupdate ; A new minute has begun
0
heinrichsweikamp
parents:
diff changeset
606
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
607 btfss divemode ; In Divemode?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
608 rcall check_nofly_desat_time ; No, so increase interval
0
heinrichsweikamp
parents:
diff changeset
609
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
610 ; Check if a new hour has just begun
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
611 tstfsz mins ; mins == 0?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
612 bra isr_rtcc2 ; No
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
613 bsf onehourupdate ; Yes, set flag
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
614
0
heinrichsweikamp
parents:
diff changeset
615 isr_rtcc2:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
616 banksel isr_backup ; Back to Bank0 ISR data
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
617 return ; Done.
0
heinrichsweikamp
parents:
diff changeset
618
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
619 isr_update_lastdive_time: ; called every second when not in divemode
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
620 ; update uptime
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
621 banksel lastdive_time+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
622 incf lastdive_time+0,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
623 movlw .0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
624 addwfc lastdive_time+1,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
625 addwfc lastdive_time+2,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
626 addwfc lastdive_time+3,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
627 banksel common
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
628 return
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
629
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
630 isr_battery_gauge:
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
631 banksel isr_backup ; Bank0 ISR data
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
632 movlw current_sleepmode ; 100µA/3600 -> nAs (Sleepmode current)
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
633 movwf isr1_temp ; Store value (low byte)
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
634 clrf isr2_temp ; High byte
0
heinrichsweikamp
parents:
diff changeset
635
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
636 banksel common ; flag1 is in Bank1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
637 btfss sleepmode ; in Sleepmode?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
638 rcall isr_battery_gauge2 ; No, compute current consumption value into isr1_temp and isr2_temp
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
639
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
640 banksel isr_backup ; Bank0 ISR data
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
641 movf isr1_temp,W ; 48Bit add of isr1_temp and isr2_temp into battery_gauge:6
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
642 addwf battery_gauge+0,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
643 movf isr2_temp,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
644 addwfc battery_gauge+1,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
645 movlw .0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
646 addwfc battery_gauge+2,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
647 addwfc battery_gauge+3,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
648 addwfc battery_gauge+4,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
649 addwfc battery_gauge+5,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
650 return
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
651
0
heinrichsweikamp
parents:
diff changeset
652 isr_battery_gauge2:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
653 ; set consumption rate in nAs for an one second interval
0
heinrichsweikamp
parents:
diff changeset
654 ; Example:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
655 ; movlw LOW .55556 ; 0,2A/3600*1e9s = nAs
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
656 ; movwf isr1_temp ; Low byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
657 ; movlw HIGH .55556 ; 0,2A/3600*1e9s = nAs
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
658 ; movwf isr2_temp ; High byte
0
heinrichsweikamp
parents:
diff changeset
659
heinrichsweikamp
parents:
diff changeset
660 ; Current consumption for LED backlight is 47*CCPR1L+272
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
661 movf CCPR1L,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
662 mullw current_backlight_multi
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
663 movlw LOW current_backlight_offset
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
664 addwf PRODL,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
665 movlw HIGH current_backlight_offset
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
666 addwfc PRODH,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
667 movff PRODL,isr1_temp
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
668 movff PRODH,isr2_temp ; isr1_temp and isr2_temp hold value for backlight
0
heinrichsweikamp
parents:
diff changeset
669
heinrichsweikamp
parents:
diff changeset
670 ; Add current for CPU and GPU
heinrichsweikamp
parents:
diff changeset
671 ; speed_setting=1: ECO (3,1mA -> 861nAs), =2: NORMAL (5,50mA -> 1528nAs) or =3: FASTEST (8,04mA -> 2233nAs)
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
672 banksel isr_backup ; Bank0 ISR data
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
673 movlw .1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
674 cpfseq speed_setting
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
675 bra isr_battery_gauge3
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
676 movlw LOW current_speed_eco
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
677 addwf isr1_temp,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
678 movlw HIGH current_speed_eco
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
679 addwfc isr2_temp,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
680 bra isr_battery_gauge5
0
heinrichsweikamp
parents:
diff changeset
681 isr_battery_gauge3:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
682 movlw .2
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
683 cpfseq speed_setting
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
684 bra isr_battery_gauge4
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
685 movlw LOW current_speed_normal
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
686 addwf isr1_temp,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
687 movlw HIGH current_speed_normal
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
688 addwfc isr2_temp,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
689 bra isr_battery_gauge5
0
heinrichsweikamp
parents:
diff changeset
690 isr_battery_gauge4:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
691 movlw LOW current_speed_fastest
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
692 addwf isr1_temp,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
693 movlw HIGH current_speed_fastest
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
694 addwfc isr2_temp,F
0
heinrichsweikamp
parents:
diff changeset
695 isr_battery_gauge5:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
696 ; Add current if IR receiver is on
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
697 btfss ir_power ; IR enabled?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
698 bra isr_battery_gauge6 ; no
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
699 movlw LOW current_ir_receiver
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
700 addwf isr1_temp,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
701 movlw HIGH current_ir_receiver
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
702 addwfc isr2_temp,F
0
heinrichsweikamp
parents:
diff changeset
703 isr_battery_gauge6:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
704 ; Add current for compass/accelerometer
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
705 btfss compass_enabled ; compass active?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
706 bra isr_battery_gauge7 ; no
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
707 movlw LOW current_compass
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
708 addwf isr1_temp,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
709 movlw HIGH current_compass
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
710 addwfc isr2_temp,F
0
heinrichsweikamp
parents:
diff changeset
711 isr_battery_gauge7:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
712 return
0
heinrichsweikamp
parents:
diff changeset
713
heinrichsweikamp
parents:
diff changeset
714 isr_divemode_1sec:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
715 incf samplesecs,F ; "samplingrate" diving seconds done
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
716 decf samplesecs_value,W ; holds "samplingrate" value (minus 1 into WREG)
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
717 cpfsgt samplesecs ; Done?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
718 bra isr_divemode_1sec2 ; no
0
heinrichsweikamp
parents:
diff changeset
719
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
720 clrf samplesecs ; clear counter...
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
721 bsf store_sample ; ...and set bit for profile storage
0
heinrichsweikamp
parents:
diff changeset
722 isr_divemode_1sec2:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
723 ; Increase re-setable average depth divetime counter
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
724 infsnz average_divesecs+0,F ; increase stopwatch registers
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
725 incf average_divesecs+1,F ; increase stopwatch registers
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
726 ; Increase total divetime (Regardless of start_dive_threshold)
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
727 infsnz total_divetime_seconds+0,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
728 incf total_divetime_seconds+1,F ; Total dive time (Regardless of start_dive_threshold)
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
729
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
730 btfss divemode2 ; displayed divetime is running?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
731 return ; No (e.g. too shallow)
0
heinrichsweikamp
parents:
diff changeset
732
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
733 ; increase divetime registers (Displayed dive time)
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
734 incf divesecs,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
735 movlw d'59'
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
736 cpfsgt divesecs
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
737 bra isr_divemode_1sec2a
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
738
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
739 clrf divesecs
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
740 bsf realdive ; this bit is always set (again) if the dive is longer then one minute
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
741 infsnz divemins+0,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
742 incf divemins+1,F ; increase divemins
0
heinrichsweikamp
parents:
diff changeset
743
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
744 isr_divemode_1sec2a:
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
745 btfss FLAG_apnoe_mode ; Are we in Apnoe mode?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
746 return ; No
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
747
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
748 incf apnoe_secs,F ; increase descent registers
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
749 movlw d'59'
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
750 cpfsgt apnoe_secs ; full minute?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
751 return ; No
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
752 clrf apnoe_secs
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
753 incf apnoe_mins,F ; increase descent mins
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
754 return
0
heinrichsweikamp
parents:
diff changeset
755
heinrichsweikamp
parents:
diff changeset
756 ;=============================================================================
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
757 ; BCD to Binary conversion.
0
heinrichsweikamp
parents:
diff changeset
758 ; Input: isr1_temp = Value in BCD
heinrichsweikamp
parents:
diff changeset
759 ; Output WREG = value in binary.
heinrichsweikamp
parents:
diff changeset
760 isr_rtcc_convert:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
761 swapf isr1_temp, W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
762 andlw 0x0F ; W = tens
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
763 rlncf WREG, W ; W = 2*tens
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
764 subwf isr1_temp, F ; 16*tens + ones - 2*tens
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
765 subwf isr1_temp, F ; 14*tens + ones - 2*tens
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
766 subwf isr1_temp, W ; 12*tens + ones - 2*tens
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
767 return
0
heinrichsweikamp
parents:
diff changeset
768
heinrichsweikamp
parents:
diff changeset
769 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
770
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
771 isr_switch_right:
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
772 bcf INTCON,INT0IE ; Disable INT0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
773 banksel common ; flag1 is in Bank1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
774 btfss flip_screen ; 180° flipped?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
775 bsf switch_right ; Set flag
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
776 btfsc flip_screen ; 180° flipped?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
777 bsf switch_left ; Set flag
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
778 bra isr_switch_common ; Continue...
0
heinrichsweikamp
parents:
diff changeset
779
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
780 isr_switch_left:
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
781 bcf INTCON3,INT1IE ; Disable INT1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
782 banksel common ; flag1 is in Bank1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
783 btfss flip_screen ; 180° flipped?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
784 bsf switch_left ; Set flag
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
785 btfsc flip_screen ; 180° flipped?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
786 bsf switch_right ; Set flag
0
heinrichsweikamp
parents:
diff changeset
787 isr_switch_common:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
788 ; load timer1 for first press
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
789 clrf TMR1L
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
790 movlw TMR1H_VALUE_FIRST ; in steps of 7,8125ms
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
791 movwf TMR1H
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
792 bsf T1CON,TMR1ON ; Start Timer 1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
793 banksel isr_backup ; Select Bank0 for ISR data.
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
794 bcf INTCON3,INT1IF ; Clear flag
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
795 bcf INTCON,INT0IF ; Clear flag
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
796 return
0
heinrichsweikamp
parents:
diff changeset
797
heinrichsweikamp
parents:
diff changeset
798 timer1int:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
799 bcf PIR1,TMR1IF ; Clear flag
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
800 banksel common ; flag1 is in Bank1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
801 bcf INTCON,INT0IF ; Clear flag
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
802 bcf INTCON3,INT1IF ; Clear flag
451
66049b6f2c0b speedup analog presses
heinrichsweikamp
parents: 448
diff changeset
803 ; digital
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
804 btfss switch_left1 ; Left button hold-down?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
805 bra timer1int_left ; Yes
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
806 btfss switch_right2 ; Right button hold-down?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
807 bra timer1int_right ; Yes
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
808
451
66049b6f2c0b speedup analog presses
heinrichsweikamp
parents: 448
diff changeset
809 ; Analog
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
810 btfsc analog_sw2_pressed ; Left button hold-down?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
811 bra timer1int_left ; Yes
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
812 btfsc analog_sw1_pressed ; Right button hold-down?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
813 bra timer1int_right ; Yes
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
814
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
815 ; No button hold-down, stop Timer 1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
816 bcf T1CON,TMR1ON ; Stop Timer 1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
817 bsf INTCON,INT0IE ; Enable INT0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
818 bsf INTCON3,INT1IE ; Enable INT1
451
66049b6f2c0b speedup analog presses
heinrichsweikamp
parents: 448
diff changeset
819 return
0
heinrichsweikamp
parents:
diff changeset
820
heinrichsweikamp
parents:
diff changeset
821 timer1int_left:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
822 btfss flip_screen ; 180° flipped?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
823 bsf switch_left ; (Re-)Set flag
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
824 btfsc flip_screen ; 180° flipped?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
825 bsf switch_right ; (Re-)Set flag
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
826 bra timer1int_common ; Continue
0
heinrichsweikamp
parents:
diff changeset
827 timer1int_right:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
828 btfss flip_screen ; 180° flipped?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
829 bsf switch_right ; Set flag
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
830 btfsc flip_screen ; 180° flipped?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
831 bsf switch_left ; Set flag
0
heinrichsweikamp
parents:
diff changeset
832 timer1int_common:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
833 ; load timer1 for next press
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
834 clrf TMR1L
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
835 movlw TMR1H_VALUE_CONT ; Surface mode
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
836 btfsc divemode
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
837 movlw TMR1H_VALUE_CONT_DIVE ; Dive mode
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
838 movwf TMR1H
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
839 return ; Return from timer1int with timer1 kept running
0
heinrichsweikamp
parents:
diff changeset
840
heinrichsweikamp
parents:
diff changeset
841 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
842
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
843 check_nofly_desat_time: ; called every minute when not in divemode
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
844 banksel int_O_desaturation_time
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
845 movf int_O_desaturation_time+0,W ; Is Desat null ?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
846 iorwf int_O_desaturation_time+1,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
847 bz check_nofly_desat_time_1 ; yes...
0
heinrichsweikamp
parents:
diff changeset
848
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
849 ; int_O_desaturation_time is only computed while in start, surface mode, menue_tree or ghostwriter.
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
850 ; So the ISR may clock surface_interval past the actual surface interval time. But TFT_surface_lastdive
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
851 ; will check int_O_desaturation_time and in case int_O_desaturation_time is zero it will not show
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
852 ; surface_interval but lastdive_time instead. So this glitch remains invisible.
0
heinrichsweikamp
parents:
diff changeset
853
147
fdd4e30846ae some cleanup
heinrichsweikamp
parents: 145
diff changeset
854 ; Increase surface interval timer
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
855 banksel common
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
856 infsnz surface_interval+0,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
857 incf surface_interval+1,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
858 return ; Done
0
heinrichsweikamp
parents:
diff changeset
859
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
860 check_nofly_desat_time_1:
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
861 banksel common
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
862 clrf surface_interval+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
863 clrf surface_interval+1 ; Clear surface interval timer
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
864 return ; Done.
0
heinrichsweikamp
parents:
diff changeset
865
heinrichsweikamp
parents:
diff changeset
866 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
867
heinrichsweikamp
parents:
diff changeset
868 isr_restore_clock:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
869 banksel isr_backup
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
870 movlw d'1'
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
871 cpfseq speed_setting
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
872 bra isr_restore_speed2
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
873 ; Reset to eco
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
874 movlw b'00000000'
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
875 movwf OSCTUNE ; 4x PLL Disable (Bit6) - only works with 8 or 16MHz (=32 or 64MHz)
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
876 movlw b'00110010'
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
877 movwf OSCCON ; 1MHz INTOSC
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
878 movlw T2CON_ECO
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
879 movwf T2CON
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
880 bra isr_restore_exit
0
heinrichsweikamp
parents:
diff changeset
881 isr_restore_speed2:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
882 movlw d'2'
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
883 cpfseq speed_setting
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
884 bra isr_restore_speed3
0
heinrichsweikamp
parents:
diff changeset
885 ; Reset to normal
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
886 movlw b'01110010'
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
887 movwf OSCCON ; 16MHz INTOSC
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
888 movlw b'00000000'
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
889 movwf OSCTUNE ; 4x PLL Disable (Bit6) - only works with 8 or 16MHz (=32 or 64MHz)
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
890 movlw T2CON_NORMAL
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
891 movwf T2CON
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
892 bra isr_restore_exit
0
heinrichsweikamp
parents:
diff changeset
893
heinrichsweikamp
parents:
diff changeset
894 isr_restore_speed3:
heinrichsweikamp
parents:
diff changeset
895 ; Reset to fastest
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
896 movlw b'01110010' ; 16MHz INTOSC
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
897 movwf OSCCON
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
898 movlw b'01000000'
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
899 movwf OSCTUNE ; 4x PLL Enable (Bit6) - only works with 8 or 16MHz (=32 or 64MHz)
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
900 movlw T2CON_FASTEST
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
901 movwf T2CON
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
902 ;bra isr_restore_exit
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
903
0
heinrichsweikamp
parents:
diff changeset
904 isr_restore_exit:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
905 btfss OSCCON,HFIOFS
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
906 bra isr_restore_exit ; loop until PLL is stable
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
907 return
0
heinrichsweikamp
parents:
diff changeset
908
410
d3087a8ed7e1 BUGFIX: Fix rare issue after battery change (OSTC3 did not start properly)
heinrichsweikamp
parents: 378
diff changeset
909
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
910 restore_flash: ; Restore first flash page from eeprom
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
911 banksel common
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
912 ; Start address in internal flash
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
913 movlw 0x00
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
914 movwf TBLPTRL
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
915 movwf TBLPTRH
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
916 movwf TBLPTRU
410
d3087a8ed7e1 BUGFIX: Fix rare issue after battery change (OSTC3 did not start properly)
heinrichsweikamp
parents: 378
diff changeset
917
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
918 movlw b'10010100' ; Setup erase
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
919 rcall Write ; Write!
410
d3087a8ed7e1 BUGFIX: Fix rare issue after battery change (OSTC3 did not start properly)
heinrichsweikamp
parents: 378
diff changeset
920
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
921 movlw .128
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
922 movwf lo ; Byte counter
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
923 clrf EEADR
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
924 movlw .3
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
925 movwf EEADRH ; Setup backup address
410
d3087a8ed7e1 BUGFIX: Fix rare issue after battery change (OSTC3 did not start properly)
heinrichsweikamp
parents: 378
diff changeset
926
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
927 TBLRD*- ; Dummy read to be in 128 byte block
410
d3087a8ed7e1 BUGFIX: Fix rare issue after battery change (OSTC3 did not start properly)
heinrichsweikamp
parents: 378
diff changeset
928 restore_flash_loop:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
929 call read_eeprom
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
930 incf EEADR,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
931 movff EEDATA,TABLAT ; put 1 byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
932 tblwt+* ; Table Write with Pre-Increment
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
933 decfsz lo,F ; 128byte done?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
934 bra restore_flash_loop ; No
410
d3087a8ed7e1 BUGFIX: Fix rare issue after battery change (OSTC3 did not start properly)
heinrichsweikamp
parents: 378
diff changeset
935
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
936 movlw b'10000100' ; Setup writes
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
937 rcall Write ; Write!
410
d3087a8ed7e1 BUGFIX: Fix rare issue after battery change (OSTC3 did not start properly)
heinrichsweikamp
parents: 378
diff changeset
938
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
939 reset ; Done, reset CPU
410
d3087a8ed7e1 BUGFIX: Fix rare issue after battery change (OSTC3 did not start properly)
heinrichsweikamp
parents: 378
diff changeset
940
d3087a8ed7e1 BUGFIX: Fix rare issue after battery change (OSTC3 did not start properly)
heinrichsweikamp
parents: 378
diff changeset
941 Write:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
942 movwf EECON1 ; Type of memory to write in
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
943 movlw 0x55
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
944 movwf EECON2
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
945 movlw 0xAA
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
946 movwf EECON2
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
947 bsf EECON1,WR ; Write
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
948 nop
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
949 nop
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
950 return
410
d3087a8ed7e1 BUGFIX: Fix rare issue after battery change (OSTC3 did not start properly)
heinrichsweikamp
parents: 378
diff changeset
951
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
952 END