annotate src/eeprom_rs232.asm @ 632:0347acdf6d8e

changelog updates
author heinrichsweikamp
date Sat, 29 Feb 2020 16:57:45 +0100
parents 185ba2f91f59
children 4050675965ea
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1 ;=============================================================================
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2 ;
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3 ; File eeprom_rs232.asm combined next generation V3.08.8
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4 ;
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5 ; Internal EEPROM, RS232
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6 ;
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7 ; Copyright (c) 2011, JD Gascuel, HeinrichsWeikamp, all right reserved.
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8 ;=============================================================================
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9 ; HISTORY
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10 ; 2011-08-06 : [mH] moving from OSTC code
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11
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12 #include "hwos.inc"
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13 #include "wait.inc"
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14 #include "shared_definitions.h"
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15 #include "rtc.inc"
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16 #include "external_flash.inc"
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17
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18 #DEFINE INSIDE_EEPROM_RS232
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19 #include "eeprom_rs232.inc"
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20
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21
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22 extern lt2942_charge_done
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23
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24 ;-----------------------------------------------------------------------------
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25 ;
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26 ; for EEPROM Macros and Memory Map, see eeprom_rs232.inc
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27 ;
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28 ;-----------------------------------------------------------------------------
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29
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30 ee_rs232 CODE
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31
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32 ;=============================================================================
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33 ; EEPROM Functions
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34 ;=============================================================================
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35
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36 ;-----------------------------------------------------------------------------
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37 ; read from internal EEPROM
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38 ;
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39 ; Input: EEADRH:EEADR = EEPROM address
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40 ; Output: EEDATA
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41 ; Trashed: NONE
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42 ;
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43 global read_eeprom
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44 read_eeprom:
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45 bcf EECON1,EEPGD ;
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46 bcf EECON1,CFGS ;
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47 bsf EECON1,RD ;
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48 return
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49
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50 ;-----------------------------------------------------------------------------
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51 ; write into internal EEPROM
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52 ;
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53 ; Input: EEADRH:EEADR = EEPROM address
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54 ; EEDATA = byte to write
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55 ; Trashed: WREG
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56 ;
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57 global write_eeprom
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58 write_eeprom:
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59 bcf EECON1,EEPGD ;
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60 bcf EECON1,CFGS ;
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61 bsf EECON1,WREN ;
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62 bcf INTCON,GIE ; disable interrupts for the next 5 instructions
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63 movlw 0x55 ; unlock sequence
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64 movwf EECON2 ; ...
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65 movlw 0xAA ; ...
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66 movwf EECON2 ; ...
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67 bsf EECON1,WR ; start write operation
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68 write_eeprom_loop:
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69 btfsc EECON1,WR ; write completed?
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70 bra write_eeprom_loop ; NO - loop waiting
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71 bcf EECON1,WREN ;
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72 bsf INTCON,GIE ; ...but the flag for the ISR routines were still set, so they will interrupt now!
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73 return
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74
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75 ;-----------------------------------------------------------------------------
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76 ; these 2 functions are meant to be used through the macros, see eeprom_rs232!
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77 ;
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78 global eeprom_read_common
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79 eeprom_read_common:
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80 movwf eeprom_loop ; initialize loop counter
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81 eeprom_read_common_loop:
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82 rcall read_eeprom ; execute read
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83 movff EEDATA,POSTINC1 ; copy byte from EEPROM data register to memory
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84 incf EEADR,F ; advance to next EEPROM cell
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85 decfsz eeprom_loop,F ; decrement loop counter, all done?
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86 bra eeprom_read_common_loop ; NO - loop
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87 return ; YES - done
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88
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89 global eeprom_write_common
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90 eeprom_write_common:
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91 movwf eeprom_loop ; initialize loop counter
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92 eeprom_write_common_loop:
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93 movff POSTINC1,EEDATA ; copy byte from memory to EEPROM data register
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94 rcall write_eeprom ; execute write
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95 incf EEADR,F ; advance to next EEPROM cell
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96 decfsz eeprom_loop,F ; decrement loop counter, all done?
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97 bra eeprom_write_common_loop ; NO - loop
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98 return ; YES - done
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99
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100 ;-----------------------------------------------------------------------------
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101 ; REad OSTC serial number
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102 ;
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103 global eeprom_serial_number_read
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104 eeprom_serial_number_read:
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105 EEPROM_II_READ eeprom_ostc_serial,mpr
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106 return
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107
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108 ;-----------------------------------------------------------------------------
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109 ; Read and write dive number offset
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110 ;
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111 global eeprom_log_offset_read
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112 eeprom_log_offset_read:
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113 EEPROM_II_READ eeprom_log_offset,mpr
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114 return
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115
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116 global eeprom_log_offset_write
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117 eeprom_log_offset_write:
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118 EEPROM_II_WRITE mpr,eeprom_log_offset
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119 return
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120
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121
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122 ;-----------------------------------------------------------------------------
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123 ; Read and write total number of dives
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124 ;
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125 global eeprom_total_dives_read
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126 eeprom_total_dives_read:
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127 EEPROM_II_READ eeprom_num_dives,mpr
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128 return
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129
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130 global eeprom_total_dives_write
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131 eeprom_total_dives_write:
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132 EEPROM_II_WRITE mpr,eeprom_num_dives
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133 return
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134
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135
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136 ;-----------------------------------------------------------------------------
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137 ; Read and write the battery gauge and type
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138 ;
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139 global eeprom_battery_gauge_read
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140 eeprom_battery_gauge_read:
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141 ; retrieve battery gauge from EEPROM 0x07-0x0C
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142 bsf block_battery_gauge ; suspend ISR from accessing the battery gauge
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143 EEPROM_CC_READ eeprom_battery_type, battery_type ; 1 byte read from EEPROM
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144 EEPROM_RR_READ eeprom_battery_gauge,battery_gauge,.6 ; 6 byte read from EEPROM
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145 bcf block_battery_gauge ; allow ISR to access the battery gauge again
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146 return
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147
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148 global eeprom_battery_gauge_write
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149 eeprom_battery_gauge_write:
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150 bsf block_battery_gauge ; suspend ISR from accessing the battery gauge
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151 EEPROM_CC_WRITE battery_type, eeprom_battery_type ; 1 byte write to EEPROM
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152 update_battery_gauge:
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153 EEPROM_RR_WRITE battery_gauge,eeprom_battery_gauge,.6 ; 6 byte write to EEPROM
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154 bcf block_battery_gauge ; allow ISR to access the battery gauge again
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155 return
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156
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157
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158 ;-----------------------------------------------------------------------------
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159 ; Read and write the deco status
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160 ;
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161 global eeprom_deco_data_read
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162 eeprom_deco_data_read:
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163
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164 btfsc RCON,POR ; was there a power outage ?
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165 bra eeprom_deco_data_read_1 ; NO - RTC is up-to-date
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166
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167 EEPROM_RR_READ eeprom_deco_data_timestamp,rtc_latched_year,.6 ; 6 byte read from EEPROM
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168 call rtc_set_rtc ; recover RTC to last known time & date
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169
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170 eeprom_deco_data_read_1:
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171
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172 ; restore surface interval
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173 EEPROM_II_READ eeprom_deco_data_surfinterval,mpr ; 2 byte read from EEPROM
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174 SMOVII mpr,surface_interval_mins ; ISR-safe copy of surface interval
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175
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176 ; bank 3: restore desaturation status
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177 EEPROM_RR_READ eeprom_deco_data_bank3,0x300,.9 ; 9 byte read from EEPROM
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178
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179 ; bank 5: restore CNS
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180 EEPROM_RR_READ eeprom_deco_data_bank5,0x500,.4 ; 4 byte read from EEPROM
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
181
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
182 ; bank 7: restore tissue pressures
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
183 EEPROM_RR_READ eeprom_deco_data_bank7,0x700,.128 ; 128 byte read from EEPROM
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
184
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
185 return ; done
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
186
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
187
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
188 global eeprom_deco_data_write
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
189 eeprom_deco_data_write:
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
190
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
191 ; invalidate current data in vault
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
192 movlw DECO_DATA_INVALID_TOKEN ; deco data invalid token
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
193 EEPROM_CC_WRITE WREG,eeprom_deco_data_validity ; 1 byte write to EEPROM
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
194
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
195 ; store vault version
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
196 movlw eeprom_vault_version ; deco data format version
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
197 EEPROM_CC_WRITE WREG,eeprom_deco_data_version ; 1 byte write to EEPROM
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
198
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
199 ; store date/time
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
200 SMOVSS rtc_year,rtc_latched_year ; ISR-safe 6 byte copy of date and time
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
201 EEPROM_RR_WRITE rtc_latched_year,eeprom_deco_data_timestamp,.6 ; 6 byte write to EEPROM
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
202
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
203 ; store surface interval
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
204 SMOVII surface_interval_mins,mpr ; ISR-safe copy of surface interval
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
205 EEPROM_II_WRITE mpr,eeprom_deco_data_surfinterval ; 2 byte write to EEPROM
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
206
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
207 ; bank 3: store desaturation status
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
208 EEPROM_RR_WRITE 0x300,eeprom_deco_data_bank3,.9 ; 9 byte write to EEPROM
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
209
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
210 ; bank 5: store CNS
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
211 EEPROM_RR_WRITE 0x500,eeprom_deco_data_bank5,.4 ; 4 byte write to EEPROM
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
212
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
213 ; bank 7: store tissue pressures
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
214 EEPROM_RR_WRITE 0x700,eeprom_deco_data_bank7,.128 ; 128 byte write to EEPROM
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
215
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
216 ; indicate new valid data in vault
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
217 movlw DECO_DATA_VALID_TOKEN ; deco data valid token
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
218 EEPROM_CC_WRITE WREG,eeprom_deco_data_validity ; 1 byte write to EEPROM
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
219
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
220 return ; done
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
221
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
222
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
223
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
224 ;=============================================================================
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
225 ; RS232 Functions
623
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
226 ;=============================================================================
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
227
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 386
diff changeset
228 global disable_ir_s8
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 386
diff changeset
229 disable_ir_s8:
623
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
230 banksel TXSTA2 ; select bank for IO register access
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 386
diff changeset
231 clrf TXSTA2
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 386
diff changeset
232 clrf RCSTA2
623
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
233 banksel common ; back to bank common
629
237931377539 3.07 stable release
heinrichsweikamp
parents: 628
diff changeset
234 bcf PIE3,RC2IE ; disable RC2 INT
237931377539 3.07 stable release
heinrichsweikamp
parents: 628
diff changeset
235 bcf ir_power ; IR off
237931377539 3.07 stable release
heinrichsweikamp
parents: 628
diff changeset
236 bcf mcp_power ; power-down instrumentation amp
237931377539 3.07 stable release
heinrichsweikamp
parents: 628
diff changeset
237 bsf s8_npower ; power-down S8 digital interface
237931377539 3.07 stable release
heinrichsweikamp
parents: 628
diff changeset
238 bcf s8_digital_avail ; digital S8 interface not available
0
heinrichsweikamp
parents:
diff changeset
239 return
heinrichsweikamp
parents:
diff changeset
240
heinrichsweikamp
parents:
diff changeset
241
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 386
diff changeset
242 global enable_ir_s8
187
669b5d00706d CHANGE: Longer timeout (4 min) for calibration menu
heinrichsweikamp
parents: 151
diff changeset
243 enable_ir_s8:
623
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
244 ;initialize serial port2 (TRISG2)
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
245 btfsc analog_o2_input ; do we have an analog input?
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
246 bra enable_s8 ; YES - search for S8 digital input
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
247 ; NO - start IR digital input
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
248 banksel BAUDCON2 ; - select bank for IO register access
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
249 movlw b'00100000' ; - BRG16=0, inverted for IR
113
heinrichsweikamp
parents: 0
diff changeset
250 movwf BAUDCON2
623
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
251 movlw b'00100000' ; - BRGH=0, SYNC=0
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 386
diff changeset
252 movwf TXSTA2
623
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
253 movlw .102 ; - SPBRGH:SPBRG = .102 : 2403 BAUD @ 16 MHz
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 386
diff changeset
254 movwf SPBRG2
623
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
255 clrf SPBRGH2
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 386
diff changeset
256 movlw b'10010000'
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 386
diff changeset
257 movwf RCSTA2
623
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
258 banksel common ; - back to bank common
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
259 bsf ir_power ; - power-up IR
629
237931377539 3.07 stable release
heinrichsweikamp
parents: 628
diff changeset
260 btfss ir_power ; - power-up confirmed?
237931377539 3.07 stable release
heinrichsweikamp
parents: 628
diff changeset
261 bra $-6 ; NO - loop and wait
237931377539 3.07 stable release
heinrichsweikamp
parents: 628
diff changeset
262 bsf PIE3,RC2IE ; - enable RC2 INT
237931377539 3.07 stable release
heinrichsweikamp
parents: 628
diff changeset
263 return ; - done
0
heinrichsweikamp
parents:
diff changeset
264
113
heinrichsweikamp
parents: 0
diff changeset
265 enable_s8:
629
237931377539 3.07 stable release
heinrichsweikamp
parents: 628
diff changeset
266 banksel TXSTA2 ; select bank for IO register access
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
267 clrf TXSTA2 ; reset UART 2 TX function
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
268 clrf RCSTA2 ; reset UART 2 RX function
623
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
269 banksel common ; back to bank common
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
270
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
271 bsf mcp_power ; power-up instrumentation amp (for analog AND digital)
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
272 btfss mcp_power ; power-up completed?
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
273 bra $-4 ; NO - loop
113
heinrichsweikamp
parents: 0
diff changeset
274
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
275 ; toggle for digital/analog
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
276 TSTOSS opt_s8_mode ; =0: analog, =1: digital RS232
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
277 bra enable_s8_analog ; -> analog
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
278
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
279 ; configure S8 digital interface
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
280 bcf s8_npower ; power S8 HUD (inverted via P-MOS transistor)
623
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
281 WAITMS d'30' ; NO - wait 30 ms
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
282 banksel BAUDCON2 ; select bank for IO register access
623
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
283 movlw b'00000000' ; BRG16=0, normal for S8
113
heinrichsweikamp
parents: 0
diff changeset
284 movwf BAUDCON2
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 386
diff changeset
285 movlw b'00100000' ; BRGH=0, SYNC=0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 386
diff changeset
286 movwf TXSTA2
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
287 movlw .25 ; SPBRGH:SPBRG = .25 : 9615 BAUD @ 16 MHz
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 386
diff changeset
288 movwf SPBRG2
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 386
diff changeset
289 movlw b'10010000'
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 386
diff changeset
290 movwf RCSTA2
623
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
291 banksel common ; back to bank common
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
292 bsf PIE3,RC2IE ; enable RC2 INT
623
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
293 bsf s8_digital_avail ; digital S8 interface available
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 386
diff changeset
294 return
113
heinrichsweikamp
parents: 0
diff changeset
295
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
296 enable_s8_analog:
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
297 ; S8 analog interface
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
298 bcf PIE3,RC2IE ; disable RC2 INT
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
299 bsf s8_npower ; power-down S8 HUD
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
300 bcf s8_digital_avail ; digital S8 interface not available
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
301 return
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
302
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
303
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
304 global ir_s8_wait_tx
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
305 ir_s8_wait_tx:
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
306 banksel TXSTA2 ; select bank for IO register access
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
307 rs232_wait_tx2_loop:
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
308 btfss TXSTA2,TRMT ; RS232 busy?
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
309 bra rs232_wait_tx2_loop ; YES - wait...
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
310 banksel common ; NO - back to bank common
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
311 return ; - done
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
312
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
313 ;-----------------------------------------------------------------------------
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 386
diff changeset
314
0
heinrichsweikamp
parents:
diff changeset
315 global enable_rs232
heinrichsweikamp
parents:
diff changeset
316 enable_rs232:
623
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
317 call request_speed_normal ; request CPU speed change to normal speed
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
318 enable_rs232_1:
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
319 btfss speed_is_normal ; speed = normal?
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
320 bra enable_rs232_1 ; NO - loop waiting for ISR to have adjusted the speed
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
321 bcf PORTE,0 ; YES - switch port to comm
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
322 bsf PORTJ,2 ; - /Reset (required for very old OSTC sport)
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
323 movlw b'00100100' ; - TX configuration: TX enabled, async, high speed
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
324 movwf TXSTA1 ; - ...
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
325 movlw b'10010000' ; - RX configuration: port enabled, RX enabled
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
326 movwf RCSTA1 ; - ...
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
327 movlw HIGH(.65536-rx_timeout*.32) ; - define TMR5H initialization value for RX timeout
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
328 movwf rx_timoeut_tmr5h_load ; - store for later use
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
329 return ; - done
0
heinrichsweikamp
parents:
diff changeset
330
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 386
diff changeset
331
0
heinrichsweikamp
parents:
diff changeset
332 global disable_rs232
heinrichsweikamp
parents:
diff changeset
333 disable_rs232:
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
334 clrf RCSTA1 ; disable RX
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
335 clrf TXSTA1 ; disable TX
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
336 bcf PORTC,6 ; switch TX pin hard to GND
623
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
337 bsf PORTE,0 ; stop comm
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
338 bcf PORTJ,2 ; /Reset (required for very old OSTC sport)
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 386
diff changeset
339 return
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 386
diff changeset
340
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 386
diff changeset
341
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
342 global rs232_wait_tx ; ++++ do not touch WREG here! ++++
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
343 rs232_wait_tx:
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
344 btfss TXSTA1,TRMT ; last byte completely shifted out on TX pin?
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
345 bra rs232_wait_tx ; NO - wait...
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
346 btfss ble_available ; YES - OSTC running with Bluetooth?
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
347 return ; NO - done
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
348 btfsc NRTS ; YES - Bluetooth module also completed TX?
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
349 bra rs232_wait_tx ; NO - wait...
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
350 return ; YES - done
623
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
351
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
352
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
353 ; ++++ make this code as fast as possible! ++++
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
354 global rs232_get_byte ; ++++ do not touch WREG here! ++++
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
355 rs232_get_byte:
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
356 bcf rs232_rx_timeout ; clear timeout flag
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
357 btfsc PIR1,RCIF ; received a data byte? (bit is set on RX complete and reset on reading RCREG1)
185ba2f91f59 3.09 beta 1 release
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358 return ; YES - done, received a byte (fast path)
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359 movff rx_timoeut_tmr5h_load,TMR5H ; - load TMR5 high with timeout value
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360 clrf TMR5L ; - load TMR5 low with a zero, writing low starts the timer
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361 bcf PIR5,TMR5IF ; - clear timer overflow flag
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362 rs232_get_byte_loop:
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363 btfsc PIR1,RCIF ; received a data byte?
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364 return ; YES - done, received a byte
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365 btfss PIR5,TMR5IF ; NO - timer overflow (timeout)?
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366 bra rs232_get_byte_loop ; NO - continue looping
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367 ;bra rs232_rx_get_timeout ; YES - give up
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368
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369 rs232_rx_get_timeout:
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370 bsf rs232_rx_timeout ; set timeout flag
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371 bcf RCSTA1,CREN ; clear receiver status by toggling CREN
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372 bsf RCSTA1,CREN ; ...
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373 return ; done, given up
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374
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375
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376 ;-----------------------------------------------------------------------------
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377 ; Send and Receive functions to be used through the macros
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378
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379 ; send a range of 1-256 bytes from memory to the RS232 interface
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380 ;
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381 global serial_tx_ram
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382 serial_tx_ram:
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383 movwf eeprom_loop ; initialize loop counter (eeprom variable used here)
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384 serial_tx_ram_loop:
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385 rcall rs232_wait_tx ; wait for completion of last transmit
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386 movff POSTINC2,TXREG1 ; send a byte from memory to serial
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387 decfsz eeprom_loop,F ; decrement loop counter, became zero?
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388 bra serial_tx_ram_loop ; NO - loop
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389 return ; YES - done
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390
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391
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392 ; receive a range of 1-256 byte from the RS232 interface and write them to memory
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393 ;
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394 global serial_rx_stream_ram ; ++++ make this code as fast as possible! ++++
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395 serial_rx_stream_ram:
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396 movwf eeprom_loop ; initialize loop counter (eeprom variable used here)
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397 serial_rx_stream_ram_loop_1:
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398 btfss PIR1,RCIF ; received a data byte? (bit is set on RX complete and reset on reading RCREG1)
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399 bra serial_rx_stream_ram_tmr ; NO - enter loop with timeout
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400 movff RCREG1,POSTINC2 ; YES - copy received byte to memory
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401 decfsz eeprom_loop,F ; - decrement loop counter, became zero?
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402 bra serial_rx_stream_ram_loop_1 ; NO - loop
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403 bcf rs232_rx_timeout ; YES - clear timeout flag
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404 return ; - all bytes received, done
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405 serial_rx_stream_ram_tmr:
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406 movff rx_timoeut_tmr5h_load,TMR5H ; load TMR5 high with timeout value
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407 clrf TMR5L ; load TMR5 low with a zero, writing low starts the timer
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408 bcf PIR5,TMR5IF ; clear timer overflow flag
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409 serial_rx_stream_ram_loop_2a:
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410 clrf TMR5L ; restart timer (see above)
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411 serial_rx_stream_ram_loop_2b:
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412 btfss PIR1,RCIF ; received a data byte? (bit is set on RX complete and reset on reading RCREG1)
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413 bra serial_rx_stream_ram_chk ; NO - check timeout
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414 movff RCREG1,POSTINC2 ; YES - copy received byte to memory
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415 decfsz eeprom_loop,F ; - decrement loop counter, became zero?
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416 bra serial_rx_stream_ram_loop_2a; NO - loop
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417 bcf rs232_rx_timeout ; YES - clear timeout flag
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418 return ; - all bytes received, done
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419 serial_rx_stream_ram_chk:
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420 btfss PIR5,TMR5IF ; timer overflow (timeout)?
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421 bra serial_rx_stream_ram_loop_2b; NO - continue looping
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422 bra rs232_rx_get_timeout ; YES - give up
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423
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424 ;-----------------------------------------------------------------------------
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425 END