annotate src/wait.asm @ 585:00ad4ffd915b

CNS Fix2
author heinrichsweikamp
date Wed, 28 Feb 2018 16:24:18 +0100
parents b455b31ce022
children ca4556fb60b9
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
0
heinrichsweikamp
parents:
diff changeset
1 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
2 ;
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 275
diff changeset
3 ; File wait.asm V2.98
0
heinrichsweikamp
parents:
diff changeset
4 ;
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 275
diff changeset
5 ; Wait routines
0
heinrichsweikamp
parents:
diff changeset
6 ;
heinrichsweikamp
parents:
diff changeset
7 ; Copyright (c) 2011, JD Gascuel, HeinrichsWeikamp, all right reserved.
heinrichsweikamp
parents:
diff changeset
8 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
9 ; HISTORY
heinrichsweikamp
parents:
diff changeset
10 ; 2004-01-31 : [chsw] Initial version.
heinrichsweikamp
parents:
diff changeset
11 ; 2007-05-11 : Updated (OSTC code).
heinrichsweikamp
parents:
diff changeset
12 ; 2011-10-18 : [mH] Timings tested with oscilloscope
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 275
diff changeset
13
275
653a3ab08062 rename into hwOS
heinrichsweikamp
parents: 0
diff changeset
14 #include "hwos.inc"
0
heinrichsweikamp
parents:
diff changeset
15
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 275
diff changeset
16 basic CODE
0
heinrichsweikamp
parents:
diff changeset
17
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 275
diff changeset
18 ; =============================================================================
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 275
diff changeset
19 ; WAIT 1 MILLISECOND (Not exact: 1,008ms +/- 30,5µs + worst case ISR latency)
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 275
diff changeset
20 ; =============================================================================
0
heinrichsweikamp
parents:
diff changeset
21
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 275
diff changeset
22 global WAITMSX
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 275
diff changeset
23 WAITMSX:
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 275
diff changeset
24 movwf wait_counter
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 275
diff changeset
25 WAITMSX2:
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 275
diff changeset
26 setf TMR5H
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 275
diff changeset
27 movlw .255-.32 ;32 x 31,5µs = 1,008ms
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 275
diff changeset
28 movwf TMR5L
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 275
diff changeset
29 bcf PIR5,TMR5IF ; Clear flag
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 275
diff changeset
30 WAITMSX3:
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 275
diff changeset
31 btfss PIR5,TMR5IF
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 275
diff changeset
32 bra WAITMSX3 ; Wait loop
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 275
diff changeset
33 decfsz wait_counter,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 275
diff changeset
34 bra WAITMSX2
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 275
diff changeset
35 return
0
heinrichsweikamp
parents:
diff changeset
36
heinrichsweikamp
parents:
diff changeset
37 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
38
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 275
diff changeset
39 END