Mercurial > public > hwos_code

annotate src/hwos.asm @ 585:00ad4ffd915b

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
CNS Fix2
author heinrichsweikamp
date Wed, 28 Feb 2018 16:24:18 +0100
parents 69a98f3f3b84
children ca4556fb60b9
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
0
heinrichsweikamp
parents:
diff changeset
1 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
2 ;
275
653a3ab08062 rename into hwOS
heinrichsweikamp
parents: 209
diff changeset
3 ; File hwos.asm
0
heinrichsweikamp
parents:
diff changeset
4 ;
275
653a3ab08062 rename into hwOS
heinrichsweikamp
parents: 209
diff changeset
5 ; Definition of the hwOS dive computer platform.
0
heinrichsweikamp
parents:
diff changeset
6 ;
heinrichsweikamp
parents:
diff changeset
7 ; Copyright (c) 2011, JD Gascuel, HeinrichsWeikamp, all right reserved.
heinrichsweikamp
parents:
diff changeset
8 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
9 ; HISTORY
heinrichsweikamp
parents:
diff changeset
10 ; 2011-05-24 : [jDG] Cleanups from initial Matthias code.
heinrichsweikamp
parents:
diff changeset
11 ; 2011-06-24 : [MH] Added clock speeds.
275
653a3ab08062 rename into hwOS
heinrichsweikamp
parents: 209
diff changeset
12 #include "hwos.inc"
0
heinrichsweikamp
parents:
diff changeset
13
heinrichsweikamp
parents:
diff changeset
14 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
15 ;----------------------------- CONFIG ---------------------------------
1
heinrichsweikamp
parents: 0
diff changeset
16 CONFIG RETEN = OFF ;Disabled - Controlled by SRETEN bit
heinrichsweikamp
parents: 0
diff changeset
17 CONFIG SOSCSEL = HIGH ;High Power SOSC circuit selected
199
heinrichsweikamp
parents: 186
diff changeset
18 CONFIG XINST = OFF ;Code won't excute in extended mode...
1
heinrichsweikamp
parents: 0
diff changeset
19 CONFIG FOSC = INTIO2 ;Internal RC oscillator, no clock-out
heinrichsweikamp
parents: 0
diff changeset
20 CONFIG PLLCFG = OFF
heinrichsweikamp
parents: 0
diff changeset
21 CONFIG IESO = OFF ;Disabled
heinrichsweikamp
parents: 0
diff changeset
22 CONFIG PWRTEN = OFF ;Disabled, because incompatible with ICD3 (Ri-400)
heinrichsweikamp
parents: 0
diff changeset
23 CONFIG BOREN = ON ;Controlled with SBOREN bit
heinrichsweikamp
parents: 0
diff changeset
24 CONFIG BORV = 2 ;2.0V
heinrichsweikamp
parents: 0
diff changeset
25 CONFIG BORPWR = MEDIUM ;BORMV set to medium power level
heinrichsweikamp
parents: 0
diff changeset
26 CONFIG WDTEN = ON ;WDT controlled by SWDTEN bit setting
heinrichsweikamp
parents: 0
diff changeset
27 CONFIG WDTPS = 128 ;1:128
heinrichsweikamp
parents: 0
diff changeset
28 CONFIG RTCOSC = SOSCREF ;RTCC uses SOSC
heinrichsweikamp
parents: 0
diff changeset
29 CONFIG MCLRE = ON ;MCLR Enabled, RG5 Disabled
heinrichsweikamp
parents: 0
diff changeset
30 CONFIG CCP2MX = PORTBE ;RE7-Microcontroller Mode/RB3-All other modes
0
heinrichsweikamp
parents:
diff changeset
31 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
32 boot CODE
275
653a3ab08062 rename into hwOS
heinrichsweikamp
parents: 209
diff changeset
33 global init_ostc
0
heinrichsweikamp
parents:
diff changeset
34
275
653a3ab08062 rename into hwOS
heinrichsweikamp
parents: 209
diff changeset
35 init_ostc:
0
heinrichsweikamp
parents:
diff changeset
36 banksel common ; Bank1
heinrichsweikamp
parents:
diff changeset
37 ;init oscillator
heinrichsweikamp
parents:
diff changeset
38 movlw b'01110010'
heinrichsweikamp
parents:
diff changeset
39 movwf OSCCON ; 16MHz INTOSC
heinrichsweikamp
parents:
diff changeset
40 movlw b'00001000'
heinrichsweikamp
parents:
diff changeset
41 movwf OSCCON2 ; Secondary Oscillator running
heinrichsweikamp
parents:
diff changeset
42 movlw b'00000000'
heinrichsweikamp
parents:
diff changeset
43 movwf OSCTUNE ; 4x PLL Disable (Bit6) - only works with 8 or 16MHz (=32 or 64MHz)
heinrichsweikamp
parents:
diff changeset
44 bcf RCON,SBOREN ; Bown-Out off
heinrichsweikamp
parents:
diff changeset
45 bcf RCON,IPEN ; Priority Interrupts off
209
56276a2418f9 cleanup
heinrichsweikamp
parents: 204
diff changeset
46 clrf CM1CON ; Disable
199
heinrichsweikamp
parents: 186
diff changeset
47 banksel WDTCON
heinrichsweikamp
parents: 186
diff changeset
48 movlw b'10000000'
heinrichsweikamp
parents: 186
diff changeset
49 movwf WDTCON ; Setup Watchdog
0
heinrichsweikamp
parents:
diff changeset
50
heinrichsweikamp
parents:
diff changeset
51 ; I/O Ports
heinrichsweikamp
parents:
diff changeset
52 banksel 0xF16 ; Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM.
heinrichsweikamp
parents:
diff changeset
53
heinrichsweikamp
parents:
diff changeset
54 clrf REFOCON ; No reference oscillator active on REFO pin
heinrichsweikamp
parents:
diff changeset
55 clrf ODCON1 ; Disable Open Drain capability
heinrichsweikamp
parents:
diff changeset
56 clrf ODCON2 ; Disable Open Drain capability
heinrichsweikamp
parents:
diff changeset
57 clrf ODCON3 ; Disable Open Drain capability
209
56276a2418f9 cleanup
heinrichsweikamp
parents: 204
diff changeset
58 clrf CM2CON ; Disable
56276a2418f9 cleanup
heinrichsweikamp
parents: 204
diff changeset
59 clrf CM3CON ; Disable
0
heinrichsweikamp
parents:
diff changeset
60
heinrichsweikamp
parents:
diff changeset
61 movlw b'11000000' ; ANSEL, AN7 and AN6 -> Analog inputs, PORTA is digital.
heinrichsweikamp
parents:
diff changeset
62 movwf ANCON0
113
heinrichsweikamp
parents: 77
diff changeset
63 movlw b'00000111' ; ANSEL, AN8, AN9, AN10 -> Analog in
0
heinrichsweikamp
parents:
diff changeset
64 movwf ANCON1
heinrichsweikamp
parents:
diff changeset
65 movlw b'00000010' ; ANSEL, AN17 -> Analog input
heinrichsweikamp
parents:
diff changeset
66 movwf ANCON2
heinrichsweikamp
parents:
diff changeset
67
heinrichsweikamp
parents:
diff changeset
68 banksel common
heinrichsweikamp
parents:
diff changeset
69
448
aadfe9f2edaf work on new battery options
heinrichsweikamp
parents: 383
diff changeset
70 ; movlw b'00000000' ; 1= Input -> Data TFT_high
aadfe9f2edaf work on new battery options
heinrichsweikamp
parents: 383
diff changeset
71 clrf TRISA
aadfe9f2edaf work on new battery options
heinrichsweikamp
parents: 383
diff changeset
72 ; movlw b'00000000' ; Init port
aadfe9f2edaf work on new battery options
heinrichsweikamp
parents: 383
diff changeset
73 clrf PORTA
0
heinrichsweikamp
parents:
diff changeset
74
113
heinrichsweikamp
parents: 77
diff changeset
75 movlw b'00000011' ; 1= Input, (RB0, RB1) -> Switches, RB2 -> Power_MCP, RB3 -> s8_npower, RB4 -> LED_green, RB5 -> /TFT_POWER
0
heinrichsweikamp
parents:
diff changeset
76 movwf TRISB
113
heinrichsweikamp
parents: 77
diff changeset
77 movlw b'00101000' ; Init port
0
heinrichsweikamp
parents:
diff changeset
78 movwf PORTB
heinrichsweikamp
parents:
diff changeset
79
heinrichsweikamp
parents:
diff changeset
80 movlw b'10011010' ; 1= Input, (RC0, RC1) -> SOSC, RC2 -> TFT_LED_PWM, (RC3,RC4) -> I²C, RC5 -> MOSI_MS5541, (RC6, RC7) -> UART1
heinrichsweikamp
parents:
diff changeset
81 movwf TRISC
448
aadfe9f2edaf work on new battery options
heinrichsweikamp
parents: 383
diff changeset
82 ; movlw b'00000000' ; Init port
aadfe9f2edaf work on new battery options
heinrichsweikamp
parents: 383
diff changeset
83 clrf PORTC
0
heinrichsweikamp
parents:
diff changeset
84
heinrichsweikamp
parents:
diff changeset
85 movlw b'00100000' ; 1= Input, RD0 -> TFT_NCS, RD1 -> TFT_RS, RD2 -> TFT_NWR, RD3 -> TFT_RD, RD4 -> MOSI_Flash, RD5 -> MISO_Flash, RD6 -> CLK_Flash, RD7 -> TFT_NRESET
heinrichsweikamp
parents:
diff changeset
86 movwf TRISD
448
aadfe9f2edaf work on new battery options
heinrichsweikamp
parents: 383
diff changeset
87 ; movlw b'00000000' ; Init port
aadfe9f2edaf work on new battery options
heinrichsweikamp
parents: 383
diff changeset
88 clrf PORTD
0
heinrichsweikamp
parents:
diff changeset
89
448
aadfe9f2edaf work on new battery options
heinrichsweikamp
parents: 383
diff changeset
90 ; movlw b'00000000' ; 1= Input, RE1 -> Power_IR, RE2 -> CS_MCP, RE3 -> LED_blue, RE4 -> power_sw1, RE5 -> Set to 1 for cR hardware
aadfe9f2edaf work on new battery options
heinrichsweikamp
parents: 383
diff changeset
91 clrf TRISE
209
56276a2418f9 cleanup
heinrichsweikamp
parents: 204
diff changeset
92 movlw b'00110001' ; Init port
0
heinrichsweikamp
parents:
diff changeset
93 movwf PORTE
heinrichsweikamp
parents:
diff changeset
94
209
56276a2418f9 cleanup
heinrichsweikamp
parents: 204
diff changeset
95 movlw b'01111110' ; 1= Input, (RF1, RF2, RF3, RF4, RF5) -> Analog
0
heinrichsweikamp
parents:
diff changeset
96 movwf TRISF
448
aadfe9f2edaf work on new battery options
heinrichsweikamp
parents: 383
diff changeset
97 ; movlw b'00000000' ; Init port
aadfe9f2edaf work on new battery options
heinrichsweikamp
parents: 383
diff changeset
98 clrf PORTF
0
heinrichsweikamp
parents:
diff changeset
99
113
heinrichsweikamp
parents: 77
diff changeset
100 movlw b'00001110' ; 1= Input, <7:6> not implemented, RG0 -> TX3_PIEZO_CFG, RG2 -> RX2, RG3 -> AN17_RSSI, RG4 -> SOSC_OUT, RG5 -> /RESET
0
heinrichsweikamp
parents:
diff changeset
101 movwf TRISG
113
heinrichsweikamp
parents: 77
diff changeset
102 movlw b'00000001' ; Init port
0
heinrichsweikamp
parents:
diff changeset
103 movwf PORTG
heinrichsweikamp
parents:
diff changeset
104
448
aadfe9f2edaf work on new battery options
heinrichsweikamp
parents: 383
diff changeset
105 ; movlw b'00000000' ; 1= Input -> Data TFT_low
aadfe9f2edaf work on new battery options
heinrichsweikamp
parents: 383
diff changeset
106 clrf TRISH
aadfe9f2edaf work on new battery options
heinrichsweikamp
parents: 383
diff changeset
107 ; movlw b'00000000' ; Init port
aadfe9f2edaf work on new battery options
heinrichsweikamp
parents: 383
diff changeset
108 clrf PORTH
0
heinrichsweikamp
parents:
diff changeset
109
120
e2f04bb2539c battery check in sleep
heinrichsweikamp
parents: 113
diff changeset
110 movlw b'10011011' ; 1= Input, RJ4 -> vusb_in, RJ5 -> power_sw2, RJ6 -> CLK_MS5541, RJ7 -> MISO_MS5541
0
heinrichsweikamp
parents:
diff changeset
111 movwf TRISJ
heinrichsweikamp
parents:
diff changeset
112 movlw b'00100000' ; Init port
heinrichsweikamp
parents:
diff changeset
113 movwf PORTJ
heinrichsweikamp
parents:
diff changeset
114
heinrichsweikamp
parents:
diff changeset
115
heinrichsweikamp
parents:
diff changeset
116 ; Timer 0
28
heinrichsweikamp
parents: 1
diff changeset
117 movlw b'00000001' ; Timer0 with 1:4 prescaler
0
heinrichsweikamp
parents:
diff changeset
118 movwf T0CON
heinrichsweikamp
parents:
diff changeset
119
heinrichsweikamp
parents:
diff changeset
120 ; Timer 1 - Button hold-down timer
heinrichsweikamp
parents:
diff changeset
121 movlw b'10001100' ; 32768Hz clock source, 1:1 Prescaler -> ; 30,51757813µs/bit in TMR1L:TMR1H
heinrichsweikamp
parents:
diff changeset
122 movwf T1CON
heinrichsweikamp
parents:
diff changeset
123
heinrichsweikamp
parents:
diff changeset
124 banksel 0xF16 ; Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM.
heinrichsweikamp
parents:
diff changeset
125
heinrichsweikamp
parents:
diff changeset
126 ; RTCC
heinrichsweikamp
parents:
diff changeset
127 movlw 0x55
heinrichsweikamp
parents:
diff changeset
128 movwf EECON2
heinrichsweikamp
parents:
diff changeset
129 movlw 0xAA
heinrichsweikamp
parents:
diff changeset
130 movwf EECON2
heinrichsweikamp
parents:
diff changeset
131 bsf RTCCFG,RTCWREN ; Unlock sequence for RTCWREN
heinrichsweikamp
parents:
diff changeset
132 bsf RTCCFG,RTCPTR1
heinrichsweikamp
parents:
diff changeset
133 bsf RTCCFG,RTCPTR0
heinrichsweikamp
parents:
diff changeset
134 bsf RTCCFG,RTCEN ; Module enable
heinrichsweikamp
parents:
diff changeset
135 bsf RTCCFG,RTCOE ; Output enable
heinrichsweikamp
parents:
diff changeset
136 movlw b'00000100' ; 32768Hz SOCS on RTCC pin (PORTG,4) Bit7-5: Pullups for Port D, E and J
heinrichsweikamp
parents:
diff changeset
137 movwf PADCFG1
heinrichsweikamp
parents:
diff changeset
138 movlw b'11000100'
heinrichsweikamp
parents:
diff changeset
139 movwf ALRMCFG ; 1 second alarm
heinrichsweikamp
parents:
diff changeset
140 movlw d'1'
heinrichsweikamp
parents:
diff changeset
141 movwf ALRMRPT ; Alarm repeat counter
heinrichsweikamp
parents:
diff changeset
142 movlw 0x55
heinrichsweikamp
parents:
diff changeset
143 movwf EECON2
heinrichsweikamp
parents:
diff changeset
144 movlw 0xAA
heinrichsweikamp
parents:
diff changeset
145 movwf EECON2
heinrichsweikamp
parents:
diff changeset
146 bcf RTCCFG,RTCWREN ; Lock sequence for RTCWREN
heinrichsweikamp
parents:
diff changeset
147
heinrichsweikamp
parents:
diff changeset
148 banksel common
heinrichsweikamp
parents:
diff changeset
149 ; A/D Converter
heinrichsweikamp
parents:
diff changeset
150 movlw b'00011000' ; power off ADC, select AN6
heinrichsweikamp
parents:
diff changeset
151 movwf ADCON0
heinrichsweikamp
parents:
diff changeset
152 movlw b'00100000' ; 2.048V Vref+
heinrichsweikamp
parents:
diff changeset
153 movwf ADCON1
heinrichsweikamp
parents:
diff changeset
154 movlw b'10001101' ; Right justified
heinrichsweikamp
parents:
diff changeset
155 movwf ADCON2
heinrichsweikamp
parents:
diff changeset
156
heinrichsweikamp
parents:
diff changeset
157
heinrichsweikamp
parents:
diff changeset
158 ;init serial port1 (TRISC6/7)
heinrichsweikamp
parents:
diff changeset
159 movlw b'00001000' ; BRG16=1
heinrichsweikamp
parents:
diff changeset
160 movwf BAUDCON1
heinrichsweikamp
parents:
diff changeset
161 movlw .34 ; SPBRGH:SPBRG = .34 : 114285 BAUD @ 16MHz (+0,79% Error to 115200 BAUD)
heinrichsweikamp
parents:
diff changeset
162 movwf SPBRG1 ; SPBRGH:SPBRG = .207 : 19230 BAUD @ 16MHz (-0,16% Error to 19200 BAUD)
heinrichsweikamp
parents:
diff changeset
163 clrf SPBRGH1 ;
204
heinrichsweikamp
parents: 200
diff changeset
164
heinrichsweikamp
parents: 200
diff changeset
165 clrf RCSTA1
heinrichsweikamp
parents: 200
diff changeset
166 clrf TXSTA1 ; UART disable
heinrichsweikamp
parents: 200
diff changeset
167 bcf PORTC,6 ; TX hard to GND
0
heinrichsweikamp
parents:
diff changeset
168
heinrichsweikamp
parents:
diff changeset
169 ;init serial port2 (TRISG2)
heinrichsweikamp
parents:
diff changeset
170 banksel BAUDCON2
113
heinrichsweikamp
parents: 77
diff changeset
171 movlw b'00100000' ; BRG16=0 ; inverted for IR
0
heinrichsweikamp
parents:
diff changeset
172 movwf BAUDCON2
heinrichsweikamp
parents:
diff changeset
173 movlw b'00100000' ; BRGH=0, SYNC=0
heinrichsweikamp
parents:
diff changeset
174 movwf TXSTA2
heinrichsweikamp
parents:
diff changeset
175 movlw .102 ; SPBRGH:SPBRG = .102 : 2403 BAUD @ 16MHz
heinrichsweikamp
parents:
diff changeset
176 movwf SPBRG2
heinrichsweikamp
parents:
diff changeset
177 clrf SPBRGH2
heinrichsweikamp
parents:
diff changeset
178 movlw b'10010000'
heinrichsweikamp
parents:
diff changeset
179 movwf RCSTA2
heinrichsweikamp
parents:
diff changeset
180 banksel common
heinrichsweikamp
parents:
diff changeset
181
heinrichsweikamp
parents:
diff changeset
182 ; Timer3 for IR-RX Timeout
heinrichsweikamp
parents:
diff changeset
183 clrf T3GCON ; Reset Timer3 Gate Control register
heinrichsweikamp
parents:
diff changeset
184 movlw b'10001001' ; 1:1 Prescaler -> 2seconds@32768Hz, synced
heinrichsweikamp
parents:
diff changeset
185 ; 30,51757813µs/bit in TMR3L:TMR3H
heinrichsweikamp
parents:
diff changeset
186 movwf T3CON
heinrichsweikamp
parents:
diff changeset
187
heinrichsweikamp
parents:
diff changeset
188 ; SPI Module(s)
heinrichsweikamp
parents:
diff changeset
189 ; SPI2: External Flash
heinrichsweikamp
parents:
diff changeset
190 movlw b'00110000'
heinrichsweikamp
parents:
diff changeset
191 movwf SSP2CON1
448
aadfe9f2edaf work on new battery options
heinrichsweikamp
parents: 383
diff changeset
192 ; movlw b'00000000'
aadfe9f2edaf work on new battery options
heinrichsweikamp
parents: 383
diff changeset
193 clrf SSP2STAT
0
heinrichsweikamp
parents:
diff changeset
194 ; ->0,25MHz Bit clock @1MHz mode (Eco)
heinrichsweikamp
parents:
diff changeset
195 ; -> 4MHz Bit clock @16MHz mode (Normal)
heinrichsweikamp
parents:
diff changeset
196 ; -> 16MHz Bit clock @64MHz mode (Fastest)
heinrichsweikamp
parents:
diff changeset
197
heinrichsweikamp
parents:
diff changeset
198 ; MSSP1 Module: I2C Master
heinrichsweikamp
parents:
diff changeset
199 movlw b'00101000' ; I2C Master Mode
heinrichsweikamp
parents:
diff changeset
200 movwf SSP1CON1
448
aadfe9f2edaf work on new battery options
heinrichsweikamp
parents: 383
diff changeset
201 ; movlw b'00000000'
aadfe9f2edaf work on new battery options
heinrichsweikamp
parents: 383
diff changeset
202 clrf SSP1CON2
0
heinrichsweikamp
parents:
diff changeset
203 movlw 0x27
heinrichsweikamp
parents:
diff changeset
204 movwf SSP1ADD ; 100kHz @ 16MHz Fosc
heinrichsweikamp
parents:
diff changeset
205
heinrichsweikamp
parents:
diff changeset
206 ; PWM Module(s)
heinrichsweikamp
parents:
diff changeset
207 ; PWM1 for LED dimming
heinrichsweikamp
parents:
diff changeset
208 movlw b'00001100'
heinrichsweikamp
parents:
diff changeset
209 movwf CCP1CON
heinrichsweikamp
parents:
diff changeset
210 movlw b'00000001'
heinrichsweikamp
parents:
diff changeset
211 movwf PSTR1CON ; Pulse steering disabled
heinrichsweikamp
parents:
diff changeset
212 movlw d'255'
heinrichsweikamp
parents:
diff changeset
213 movwf PR2 ; Period
heinrichsweikamp
parents:
diff changeset
214 ; 255 is max brightness (300mW)
heinrichsweikamp
parents:
diff changeset
215 clrf CCPR1L ; Duty cycle
heinrichsweikamp
parents:
diff changeset
216 clrf CCPR1H ; Duty cycle
heinrichsweikamp
parents:
diff changeset
217 movlw T2CON_NORMAL
heinrichsweikamp
parents:
diff changeset
218 movwf T2CON
heinrichsweikamp
parents:
diff changeset
219
heinrichsweikamp
parents:
diff changeset
220 ; Timer5 for ISR-independent wait routines
heinrichsweikamp
parents:
diff changeset
221 clrf T5GCON ; Reset Timer5 Gate Control register
heinrichsweikamp
parents:
diff changeset
222 movlw b'10001001' ; 1:1 Prescaler -> 2seconds@32768Hz, synced
heinrichsweikamp
parents:
diff changeset
223 ; 30,51757813µs/bit in TMR5L:TMR5H
heinrichsweikamp
parents:
diff changeset
224 movwf T5CON
heinrichsweikamp
parents:
diff changeset
225
heinrichsweikamp
parents:
diff changeset
226 ; Timer7 for 62,5ms Interrupt (Sensor states)
heinrichsweikamp
parents:
diff changeset
227 banksel 0xF16 ; Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM.
heinrichsweikamp
parents:
diff changeset
228 clrf T7GCON ; Reset Timer7 Gate Control register
heinrichsweikamp
parents:
diff changeset
229 movlw b'10001001' ; 1:1 Prescaler -> 2seconds@32768Hz, synced
heinrichsweikamp
parents:
diff changeset
230 movwf T7CON
heinrichsweikamp
parents:
diff changeset
231 clrf TMR7L
heinrichsweikamp
parents:
diff changeset
232 movlw .248
heinrichsweikamp
parents:
diff changeset
233 movwf TMR7H ; -> Rollover after 2048 cycles -> 62,5ms
heinrichsweikamp
parents:
diff changeset
234
heinrichsweikamp
parents:
diff changeset
235 banksel common
heinrichsweikamp
parents:
diff changeset
236 ; Interrupts
50
ec4d8503ec45 NEW: user-selectable color schemes
heinrichsweikamp
parents: 28
diff changeset
237 movlw b'11010000'
0
heinrichsweikamp
parents:
diff changeset
238 movwf INTCON
77
131e6dd9e201 BUGFIX: Potential bug to freeze the OSTC3 after battery change or update
heinrichsweikamp
parents: 58
diff changeset
239 movlw b'00001000' ; BIT7=1: Pullup for PORTB disabled
0
heinrichsweikamp
parents:
diff changeset
240 movwf INTCON2
77
131e6dd9e201 BUGFIX: Potential bug to freeze the OSTC3 after battery change or update
heinrichsweikamp
parents: 58
diff changeset
241 movlw b'00000000'
0
heinrichsweikamp
parents:
diff changeset
242 movwf INTCON3
heinrichsweikamp
parents:
diff changeset
243 movlw b'00000001' ; Bit0: TMR1
heinrichsweikamp
parents:
diff changeset
244 movwf PIE1
heinrichsweikamp
parents:
diff changeset
245 movlw b'00000010' ; Bit1: TMR3
heinrichsweikamp
parents:
diff changeset
246 movwf PIE2
heinrichsweikamp
parents:
diff changeset
247 movlw b'00000000' ; Bit1: TMR5
heinrichsweikamp
parents:
diff changeset
248 movwf PIE5
heinrichsweikamp
parents:
diff changeset
249 movlw b'00100001' ; Bit0: RTCC, Bit5: UART2
heinrichsweikamp
parents:
diff changeset
250 movwf PIE3
heinrichsweikamp
parents:
diff changeset
251 movlw b'00001000' ; Bit3: TMR7
heinrichsweikamp
parents:
diff changeset
252 movwf PIE5
heinrichsweikamp
parents:
diff changeset
253
501
heinrichsweikamp
parents: 463
diff changeset
254 bsf power_sw1
heinrichsweikamp
parents: 463
diff changeset
255 btfss power_sw1
heinrichsweikamp
parents: 463
diff changeset
256 bra $-4
heinrichsweikamp
parents: 463
diff changeset
257 bsf power_sw2
heinrichsweikamp
parents: 463
diff changeset
258 btfss power_sw2
heinrichsweikamp
parents: 463
diff changeset
259 bra $-4
0
heinrichsweikamp
parents:
diff changeset
260
204
heinrichsweikamp
parents: 200
diff changeset
261 movlw d'2'
319
cf929551d31c move flag13 into bank common
heinrichsweikamp
parents: 275
diff changeset
262 movff WREG,speed_setting ; Normal
204
heinrichsweikamp
parents: 200
diff changeset
263
heinrichsweikamp
parents: 200
diff changeset
264
0
heinrichsweikamp
parents:
diff changeset
265 return
heinrichsweikamp
parents:
diff changeset
266
heinrichsweikamp
parents:
diff changeset
267 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
268 global speed_eco
heinrichsweikamp
parents:
diff changeset
269 speed_eco:
heinrichsweikamp
parents:
diff changeset
270 movlw d'1'
heinrichsweikamp
parents:
diff changeset
271 movff WREG,speed_setting ; Bank-independent
heinrichsweikamp
parents:
diff changeset
272 ; Done in ISR
heinrichsweikamp
parents:
diff changeset
273 return
heinrichsweikamp
parents:
diff changeset
274 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
275 global speed_normal
heinrichsweikamp
parents:
diff changeset
276 speed_normal:
heinrichsweikamp
parents:
diff changeset
277 movlw d'2'
heinrichsweikamp
parents:
diff changeset
278 movff WREG,speed_setting ; Bank-independent
heinrichsweikamp
parents:
diff changeset
279 ; Done in ISR
heinrichsweikamp
parents:
diff changeset
280 return
heinrichsweikamp
parents:
diff changeset
281 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
282 global speed_fastest
heinrichsweikamp
parents:
diff changeset
283 speed_fastest:
heinrichsweikamp
parents:
diff changeset
284 movlw d'3'
heinrichsweikamp
parents:
diff changeset
285 movff WREG,speed_setting ; Bank-independent
heinrichsweikamp
parents:
diff changeset
286 ; Done in ISR
heinrichsweikamp
parents:
diff changeset
287 return
heinrichsweikamp
parents:
diff changeset
288 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
289
heinrichsweikamp
parents:
diff changeset
290 END